M-Labs
/
HeavyX
6
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity
Next-generation FPGA SoC toolkit
55 Commits 2 Branches 0 Tags 412 KiB
Nix 60.4%
Python 29.9%
Diff 7.1%
Rust 2.4%
RPC 0.2%
Go to file
Sebastien Bourdeauducq 05822f0a36 simplesoc_ecp5: remove nmigen/#30 workaround 2019-05-12 15:01:45 +08:00
compilers rust: add riscv32i 2019-04-09 00:48:19 +08:00
cores Update to SpinalHDL 1.3.3 VexRiscv 1.1 2019-04-28 20:49:45 +08:00
eda nmigen: bump 2019-05-12 14:58:08 +08:00
examples simplesoc_ecp5: remove nmigen/#30 workaround 2019-05-12 15:01:45 +08:00
heavycomps add wishbone components 2019-05-02 12:53:08 +08:00
.gitignore add nix-build results to .gitignore 2019-03-25 23:36:52 +08:00
default.nix add ECP5 helloworld 2019-04-26 18:22:23 +08:00
derivations.nix rust: add riscv32i 2019-04-09 00:48:19 +08:00
heavycomps.nix add component library with UART 2019-03-19 16:52:02 +08:00
release.nix add simplesoc_ecp5 to continuous build 2019-05-02 12:54:57 +08:00