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simplesoc_ecp5: disable minerva muldiv

pull/1/head
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commit
f7e7b894b7
  1. 2
      examples/simplesoc_ecp5.py

2
examples/simplesoc_ecp5.py

@ -35,7 +35,7 @@ class Top(Elaboratable):
m.domains += cd_sync
m.d.comb += cd_sync.clk.eq(self.clk100)
m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False)
m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024))
m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6)
m.submodules.con = con = wishbone.InterconnectShared(

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