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@ -35,7 +35,7 @@ class Top(Elaboratable): |
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m.domains += cd_sync |
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m.d.comb += cd_sync.clk.eq(self.clk100) |
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m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False) |
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m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False) |
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m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024)) |
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m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6) |
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m.submodules.con = con = wishbone.InterconnectShared( |
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