simplesoc_ecp5: disable minerva muldiv

2 years ago · f7e7b894b7
1 changed files with 1 additions and 1 deletions
--- a/examples/simplesoc_ecp5.py
+++ b/examples/simplesoc_ecp5.py
@ -35,7 +35,7 @@ class Top(Elaboratable):
        m.domains += cd_sync
        m.d.comb += cd_sync.clk.eq(self.clk100)

-        m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False)
+        m.submodules.cpu = cpu = Minerva(with_icache=False, with_dcache=False, with_muldiv=False)
        m.submodules.ram = ram = wishbone.SRAM(Memory(32, 1024))
        m.submodules.uart = uart = SimpleWishboneSerial(self.serial_tx, 100e6)
        m.submodules.con = con = wishbone.InterconnectShared(