Next-generation FPGA SoC toolkit
 
 
 
 
 
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Sebastien Bourdeauducq 677ddefff2 mark riscv llvm 2019-05-14 14:07:36 +08:00
compilers rust: add riscv32i 2019-04-09 00:48:19 +08:00
cores minerva: bump 2019-05-13 00:46:43 +08:00
eda nmigen: bump 2019-05-12 14:58:08 +08:00
examples simplesoc_ecp5: disable minerva muldiv 2019-05-13 00:46:52 +08:00
heavycomps add wishbone components 2019-05-02 12:53:08 +08:00
.gitignore add nix-build results to .gitignore 2019-03-25 23:36:52 +08:00
default.nix add ECP5 helloworld 2019-04-26 18:22:23 +08:00
derivations.nix mark riscv llvm 2019-05-14 14:07:36 +08:00
heavycomps.nix add component library with UART 2019-03-19 16:52:02 +08:00
release.nix add simplesoc_ecp5 to continuous build 2019-05-02 12:54:57 +08:00