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add __all__

pull/1/head
parent
commit
d765dfb7b9
  1. 3
      heavycomps/heavycomps/uart.py

3
heavycomps/heavycomps/uart.py

@ -2,6 +2,9 @@ from nmigen import *
from nmigen.lib.cdc import MultiReg
__all__ = ["RS232RX", "RS232TX"]
class RS232RX(Elaboratable):
def __init__(self, tuning_word):
self.rx = Signal()

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