add __all__

2019-05-01 17:05:19 +08:00 · 2019-05-01 17:05:19 +08:00 · d765dfb7b9
commit d765dfb7b9
parent d84b172245
1 changed files with 3 additions and 0 deletions
--- a/heavycomps/heavycomps/uart.py
+++ b/heavycomps/heavycomps/uart.py
@ -2,6 +2,9 @@ from nmigen import *
 from nmigen.lib.cdc import MultiReg


+__all__ = ["RS232RX", "RS232TX"]
+
+
 class RS232RX(Elaboratable):
    def __init__(self, tuning_word):
        self.rx = Signal()