add wishbone components
parent
88db84cfd7
commit
70638e6d87
@ -1,20 +0,0 @@
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from nmigen import *
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class RoundRobin(Elaboratable):
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def __init__(self, n):
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self.n = n
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self.request = Signal(n)
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self.grant = Signal(max=n)
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def elaborate(self, platform):
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m = Module()
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with m.Switch(self.grant):
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for i in range(self.n):
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with m.Case(i):
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with m.If(~self.request[i]):
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for j in reversed(range(i+1, i+self.n)):
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t = j % self.n
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with m.If(self.request[t]):
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m.d.sync += self.grant.eq(t)
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return m
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@ -0,0 +1,210 @@
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from enum import Enum
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from functools import reduce
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from operator import or_
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from nmigen import *
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from nmigen.hdl.rec import *
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__all__ = ["Cycle", "Interface", "Arbiter", "Decoder", "InterconnectShared"]
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class Cycle(Enum):
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CLASSIC = 0
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CONSTANT = 1
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INCREMENT = 2
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END = 7
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wishbone_layout = [
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("adr", 30, DIR_FANOUT),
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("dat_w", 32, DIR_FANOUT),
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("dat_r", 32, DIR_FANIN),
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("sel", 4, DIR_FANOUT),
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("cyc", 1, DIR_FANOUT),
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("stb", 1, DIR_FANOUT),
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("ack", 1, DIR_FANIN),
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("we", 1, DIR_FANOUT),
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("cti", 3, DIR_FANOUT),
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("bte", 2, DIR_FANOUT),
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("err", 1, DIR_FANIN)
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]
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class Interface(Record):
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def __init__(self):
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Record.__init__(self, wishbone_layout)
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def _do_transaction(self):
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yield self.cyc.eq(1)
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yield self.stb.eq(1)
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yield
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while not (yield self.ack):
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yield
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yield self.cyc.eq(0)
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yield self.stb.eq(0)
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def write(self, adr, dat, sel=None):
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if sel is None:
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sel = 2**len(self.sel) - 1
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yield self.adr.eq(adr)
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yield self.dat_w.eq(dat)
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yield self.sel.eq(sel)
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yield self.we.eq(1)
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yield from self._do_transaction()
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def read(self, adr):
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yield self.adr.eq(adr)
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yield self.we.eq(0)
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yield from self._do_transaction()
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return (yield self.dat_r)
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class SRAM(Elaboratable):
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def __init__(self, mem, read_only=False, bus=None):
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self.mem = mem
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self.read_only = read_only
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if bus is None:
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bus = Interface()
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self.bus = bus
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def elaborate(self, platform):
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m = Module()
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if self.mem.width > len(self.bus.dat_r):
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raise NotImplementedError
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# read
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m.submodules.rdport = rdport = self.mem.read_port()
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m.d.comb += [
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rdport.addr.eq(self.bus.adr[:len(rdport.addr)]),
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self.bus.dat_r.eq(rdport.data)
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]
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# write
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if not self.read_only:
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m.submodules.wrport = wrport = self.mem.write_port(granularity=8)
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m.d.comb += [
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wrport.addr.eq(self.bus.adr[:len(rdport.addr)]),
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wrport.data.eq(self.bus.dat_w)
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]
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for i in range(4):
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m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
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# generate ack
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m.d.sync += self.bus.ack.eq(0)
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with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
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m.d.sync += self.bus.ack.eq(1)
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return m
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class RoundRobin(Elaboratable):
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def __init__(self, n):
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self.n = n
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self.request = Signal(n)
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self.grant = Signal(max=n)
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def elaborate(self, platform):
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m = Module()
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with m.Switch(self.grant):
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for i in range(self.n):
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with m.Case(i):
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with m.If(~self.request[i]):
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for j in reversed(range(i+1, i+self.n)):
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t = j % self.n
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with m.If(self.request[t]):
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m.d.sync += self.grant.eq(t)
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return m
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class Arbiter(Elaboratable):
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def __init__(self, masters, target):
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self.masters = masters
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self.target = target
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def elaborate(self, platform):
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m = Module()
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m.submodules.rr = rr = RoundRobin(len(self.masters))
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# mux master->target signals
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for name, size, direction in wishbone_layout:
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if direction == DIR_FANOUT:
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choices = Array(getattr(m, name) for m in self.masters)
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m.d.comb += getattr(self.target, name).eq(choices[rr.grant])
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# connect target->master signals
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for name, size, direction in wishbone_layout:
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if direction == DIR_FANIN:
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source = getattr(self.target, name)
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for i, master in enumerate(self.masters):
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dest = getattr(master, name)
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if name == "ack" or name == "err":
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m.d.comb += dest.eq(source & (rr.grant == i))
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else:
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m.d.comb += dest.eq(source)
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# connect bus requests to round-robin selector
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reqs = [m.cyc & ~m.ack for m in self.masters]
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m.d.comb += rr.request.eq(Cat(*reqs))
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return m
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class Decoder(Elaboratable):
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def __init__(self, master, targets, register=False):
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self.master = master
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self.targets = targets
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self.register = register
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def elaborate(self, platform):
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m = Module()
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nt = len(self.targets)
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target_sel = Signal(nt)
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target_sel_r = Signal(nt)
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# decode target addresses
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for i, (fun, bus) in enumerate(self.targets):
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m.d.comb += target_sel[i].eq(fun(self.master.adr))
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if self.register:
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m.d.sync += target_sel_r.eq(target_sel)
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else:
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m.d.comb += target_sel_r.eq(target_sel)
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# connect master->targets signals except cyc
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for target in self.targets:
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for name, size, direction in wishbone_layout:
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if direction == DIR_FANOUT and name != "cyc":
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m.d.comb += getattr(target[1], name).eq(getattr(self.master, name))
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# combine cyc with target selection signals
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for i, target in enumerate(self.targets):
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m.d.comb += target[1].cyc.eq(self.master.cyc & target_sel[i])
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# generate master ack (resp. err) by ORing all target acks (resp. errs)
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m.d.comb += [
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self.master.ack.eq(reduce(or_, [target[1].ack for target in self.targets])),
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self.master.err.eq(reduce(or_, [target[1].err for target in self.targets]))
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]
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# mux (1-hot) target data return
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masked = [Repl(target_sel_r[i], len(self.master.dat_r)) & self.targets[i][1].dat_r for i in range(nt)]
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m.d.comb += self.master.dat_r.eq(reduce(or_, masked))
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return m
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class InterconnectShared(Module):
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def __init__(self, masters, targets, register=False):
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self.masters = masters
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self.targets = targets
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self.register = register
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def elaborate(self, platform):
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m = Module()
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shared = Interface()
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m.submodules.arbiter = Arbiter(self.masters, shared)
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m.submodules.decoder = Decoder(shared, self.targets, self.register)
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return m
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