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use Elaboratable

pull/1/head
parent
commit
a19f0784d0
  1. 2
      examples/helloworld_kintex7.py
  2. 2
      heavycomps/heavycomps/roundrobin.py
  3. 2
      heavycomps/heavycomps/test/test_uart.py
  4. 4
      heavycomps/heavycomps/uart.py

2
examples/helloworld_kintex7.py

@ -4,7 +4,7 @@ from nmigen.back import verilog
from heavycomps import uart
class Top:
class Top(Elaboratable):
def __init__(self, baudrate=115200):
self.baudrate = baudrate
self.clk156_p = Signal()

2
heavycomps/heavycomps/roundrobin.py

@ -1,7 +1,7 @@
from nmigen import *
class RoundRobin:
class RoundRobin(Elaboratable):
def __init__(self, n):
self.n = n
self.request = Signal(n)

2
heavycomps/heavycomps/test/test_uart.py

@ -6,7 +6,7 @@ from nmigen.back.pysim import *
from heavycomps import uart
class Loopback:
class Loopback(Elaboratable):
def __init__(self, tuning_word=2**31):
self.tx = uart.RS232TX(tuning_word)
self.rx = uart.RS232RX(tuning_word)

4
heavycomps/heavycomps/uart.py

@ -2,7 +2,7 @@ from nmigen import *
from nmigen.lib.cdc import MultiReg
class RS232RX:
class RS232RX(Elaboratable):
def __init__(self, tuning_word):
self.rx = Signal()
self.data = Signal(8)
@ -58,7 +58,7 @@ class RS232RX:
return value
class RS232TX:
class RS232TX(Elaboratable):
def __init__(self, tuning_word):
self.tx = Signal(reset=1)
self.data = Signal(8)

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