use Elaboratable
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@ -4,7 +4,7 @@ from nmigen.back import verilog
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from heavycomps import uart
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class Top:
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class Top(Elaboratable):
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def __init__(self, baudrate=115200):
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self.baudrate = baudrate
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self.clk156_p = Signal()
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@ -1,7 +1,7 @@
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from nmigen import *
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class RoundRobin:
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class RoundRobin(Elaboratable):
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def __init__(self, n):
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self.n = n
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self.request = Signal(n)
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@ -6,7 +6,7 @@ from nmigen.back.pysim import *
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from heavycomps import uart
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class Loopback:
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class Loopback(Elaboratable):
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def __init__(self, tuning_word=2**31):
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self.tx = uart.RS232TX(tuning_word)
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self.rx = uart.RS232RX(tuning_word)
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@ -2,7 +2,7 @@ from nmigen import *
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from nmigen.lib.cdc import MultiReg
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class RS232RX:
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class RS232RX(Elaboratable):
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def __init__(self, tuning_word):
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self.rx = Signal()
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self.data = Signal(8)
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@ -58,7 +58,7 @@ class RS232RX:
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return value
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class RS232TX:
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class RS232TX(Elaboratable):
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def __init__(self, tuning_word):
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self.tx = Signal(reset=1)
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self.data = Signal(8)
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