|
compilers
|
rust: add riscv32i
|
2019-04-09 00:48:19 +08:00 |
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cores
|
Update to SpinalHDL 1.3.3 VexRiscv 1.1
|
2019-04-28 20:49:45 +08:00 |
|
eda
|
nmigen: bump
|
2019-05-12 14:58:08 +08:00 |
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examples
|
ecp5: use speed grade 8 (versa)
|
2019-05-06 22:44:58 +08:00 |
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heavycomps
|
add wishbone components
|
2019-05-02 12:53:08 +08:00 |
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.gitignore
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add nix-build results to .gitignore
|
2019-03-25 23:36:52 +08:00 |
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default.nix
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add ECP5 helloworld
|
2019-04-26 18:22:23 +08:00 |
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derivations.nix
|
rust: add riscv32i
|
2019-04-09 00:48:19 +08:00 |
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heavycomps.nix
|
add component library with UART
|
2019-03-19 16:52:02 +08:00 |
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release.nix
|
add simplesoc_ecp5 to continuous build
|
2019-05-02 12:54:57 +08:00 |
