David Nadlinger
1c71ae636a
examples: Add edge counters to kasli_tester variant
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This enables test_edge_counter on the CI system.
2019-01-15 10:55:07 +00:00
David Nadlinger
67a6882e91
examples: Fix kasli_tester device_db offset comments
2019-01-15 10:55:07 +00:00
David Nadlinger
101ed5d534
examples: Fix DRTIO destination indices ( #1231 )
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Using the default routing table, links numbers and destinations
are offset by 1, as destination 0 is local RTIO.
2019-01-09 11:40:15 +08:00
Drew
d60b95f481
tdr.py: typo ( #1220 )
2018-12-18 18:47:09 +00:00
Kaifeng
cc143d5fec
kasli_tester: add support for windows platform. ( #1204 )
2018-12-05 14:06:45 +01:00
b32e89444c
Merge branch 'master' into new
2018-11-26 01:02:19 +08:00
22a223bf82
examples/master: clean up remnants of early urukul tests
2018-11-19 21:42:41 +08:00
c990b5e4f1
Merge remote-tracking branch 'origin/master' into new
2018-11-08 20:21:56 +08:00
ad0254c17b
Merge branch 'switching125' into new
2018-11-07 22:03:18 +08:00
e17e458c58
ptb2: add sync to urukul0 for ad9910 usage
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 10:06:51 +00:00
9a3d81ffee
kasli: fix tester clk_sel
2018-11-06 14:49:21 +08:00
fb12df7e01
Revert "kasli_tester: urukul0 mmcx clock defunct"
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This reverts commit 68220c316d
2018-11-06 14:33:21 +08:00
31f68ddf6c
Merge branch 'urukul-sync'
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* urukul-sync: (29 commits)
urukul: flake8 [nfc]
ad9910: flake8 [nfc]
urukul/ad9910 test: remove unused import
test_urukul: relax speed
urukul,ad9910: print speed metrics
kasli: add PTB2 (external clock and SYNC)
kasli: add sync to LUH, HUB, Opticlock
kasli_tester: urukul0 mmcx clock defunct
test_ad9910: relax ifc mode read
tests: add Urukul-AD9910 HITL unittests including SYNC
ad9910: add init bit explanation
test: add Urukul CPLD HITL tests
ad9910: fiducial timestamp for tracking phase mode
ad9910: add phase modes
ad9910: fix pll timeout loop
tester: add urukul sync
ptb: back out urukul-sync
ad9910: add IO_UPDATE alignment and tuning
urukul: set up sync_in generator
ad9910: add io_update alignment measurement
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close #1143
2018-11-05 19:54:30 +01:00
32d538f72b
kasli: add PTB2 (external clock and SYNC)
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:16 +01:00
d8a5951a13
kasli: add sync to LUH, HUB, Opticlock
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for #1143 , also add missing LUH device db
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:14 +01:00
68220c316d
kasli_tester: urukul0 mmcx clock defunct
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:11 +01:00
bc04da15c5
test: add Urukul CPLD HITL tests
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:00 +01:00
4269d5ad5c
tester: add urukul sync
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:52 +01:00
60d3bc63a7
ptb: back out urukul-sync
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... for backwards compatibility.
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:50 +01:00
0433e8f4fe
urukul: add sync_in generator
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
f755a4682a
device_db_ptb: fix zotino clr
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:24 +01:00
David Nadlinger
cbdef0225c
ttl: Add target RTIO time argument to timestamp/count functions
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Software-based tracking of timestamps is problematic (e.g. when
using DMA, see GitHub #1113 ).
2018-11-03 20:33:19 +08:00
bc4a8157c0
kasli: add tsinghua2
2018-11-01 18:26:37 +08:00
9793632282
enviromnment: rename 'save' in set_dataset to 'archive'. Closes #1171
2018-10-21 12:08:34 +08:00
6357a50d33
kasli: update nudt variant
2018-10-15 18:04:57 +08:00
969a305c5a
Merge branch 'master' into switching125
2018-10-04 10:08:42 +08:00
3b3fddb5a4
kasli: add mitll2
2018-09-27 23:21:52 +08:00
998a468983
examples: add grabber to device databases
2018-09-27 16:09:25 +08:00
20cddb6a25
tester: handle no available ttl outputs
2018-09-24 09:19:28 +00:00
c8cd830118
drtio: implement get_rtio_destination_status for kernels
2018-09-15 19:11:22 +08:00
3cbdf2fbac
kasli: cleanup drtio blink example
2018-09-15 18:43:27 +08:00
8227037a84
examples: add kasli_drtioswitching
2018-09-11 22:20:18 +08:00
bf36786d45
kasli_tester: clean up grabber test
2018-09-04 10:59:19 +00:00
e7dba34475
kasli/tester: fill all 12 EEM
2018-08-29 18:09:09 +00:00
9b6ea47b7a
kasli: use SFP LEDs to show DRTIO link status. Closes #1073
2018-08-19 13:04:41 +08:00
66e33a66d6
test: enable TTL loopback tests on Kasli
2018-08-17 13:35:55 +08:00
bc3e715a8f
examples: fix kasli_tester
2018-08-11 10:51:42 +08:00
957645a7e7
examples: move kasli tester out of kasli_basic
2018-08-09 18:07:44 +08:00
bbc98410e4
test: dds → ad9914dds
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Prevent confusion with Urukul.
2018-08-09 16:55:09 +08:00
a061ba2505
grabber/kasli_basic: add grabber test
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close #1121
2018-08-08 12:43:44 +02:00
8b8e1844f0
kasli_sawgmaster: roughly match Urukul and Sayma amplitudes
2018-08-07 20:07:21 +08:00
9ce6233926
kasli: fix SYSU TTL directions
2018-08-07 19:29:28 +08:00
8aa88cfe70
kasli_sawgmaster: add Urukul-Sayma example
2018-08-07 19:29:28 +08:00
65f198bdee
kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example
2018-08-06 16:53:13 +08:00
d152506ecb
sayma: update fmcdio_vhdci_eem demo
2018-07-19 15:47:20 +08:00
31f4f8792a
sayma: add Urukul and Zotino to example device_db
2018-07-18 10:31:55 +08:00
5e62910a8d
examples: add Sayma VHDCI DIO
2018-07-17 23:28:05 +08:00
82145b1263
examples: sayma_drtio → sayma_masterdac
2018-07-17 20:32:30 +08:00
3168b193e6
kc705: remove Zotino and Urukul
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* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
2018-07-17 17:48:57 +08:00
4420046502
kasli_tester: support mixed AD9910/AD9912 systems
2018-07-06 15:43:38 +08:00
ac3f360c26
kasli_tester: fix AD9912 support
2018-07-06 15:43:25 +08:00
509562ddbf
kasli: add WIPM target
2018-07-06 15:41:28 +08:00
0483b8d14c
sayma_drtio: ditto
2018-06-28 17:03:32 +08:00
04d6ff45c8
kasli_sawgmaster: reset SAWGs
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Most importantly this resets the phase accumulators.
2018-06-28 17:01:48 +08:00
51a5d8dff9
examples: add Kasli SAWG master
2018-06-22 18:57:49 +08:00
83428961ad
sayma: add SAWG and JESD to DRTIO master
2018-06-22 00:04:22 +08:00
5a91f820fd
examples: change Sayma sines frequency to 9MHz
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Well within Red Pitaya bandwidth.
2018-06-20 22:40:07 +08:00
9288301543
examples: add DRTIO sines
2018-06-20 22:39:40 +08:00
4803ca3799
examples/sayma_drtio: add SAWG channels
2018-06-19 23:50:26 +08:00
cae92f9b44
kasli: add Tsinghua variant
2018-06-06 19:03:45 +08:00
62deffa7d2
opticlock: fix core device name
2018-06-01 15:39:23 +00:00
f50aef1a22
suservo: extract boilerplate
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closes #1041
2018-06-01 15:37:07 +00:00
2c344686d9
ad53xx/zotino: enable overtemp shutdown and readback control
2018-06-01 13:06:52 +00:00
87d3ac9d25
suservo: swap transfer function parametrization
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The integrator is now parametrized through its gain and not the PI
corner frequency. The integrator gain limit is given in absolute gain
units and not relative to the proportional gain.
close #1033
2018-06-01 09:38:18 +00:00
8fd57e6ccb
kasli_tester: add Sampler and Zotino support
2018-05-29 22:36:42 +08:00
ad099edf63
kasli: integrate grabber
2018-05-28 22:43:40 +08:00
c2890c6cf0
kasli_tester: initialize DDS channels
2018-05-28 14:24:39 +08:00
4d3f763865
move kasli_opticlock to kasli_basic
2018-05-28 11:02:44 +08:00
b09d07905c
kasli: add LUH/PTB/HUB variants
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and refactor/simplify variant selection
2018-05-27 18:33:27 +00:00
fcd12e3472
suservo: work around #1007
2018-05-22 17:36:41 +00:00
4e5fe672e7
kasli: add tester target
2018-05-21 17:43:39 +08:00
2e6b81d59a
kasli_tester: reset core device
2018-05-21 15:35:29 +08:00
8513f0b0d4
minor cleanup
2018-05-21 15:35:00 +08:00
f953bee79e
kasli_test: add RF switch control
2018-05-18 23:48:29 +08:00
f457b59985
kasli_tester: bail out when run from ARTIQ master
2018-05-18 23:30:52 +08:00
3cbcb3bff6
move mitll, sysu and ustc device_dbs to kasli_basic
2018-05-18 23:20:40 +08:00
bdfd993818
kasli_tester: add Urukul support
2018-05-18 23:18:03 +08:00
9a4408a570
add Kasli TTL tester
2018-05-18 22:52:53 +08:00
37bd0c2566
kasli: add USTC target
2018-05-18 16:15:07 +08:00
73f8e61478
kasli_sysu: fix TTL directions in example device_db
2018-05-18 16:13:50 +08:00
a100c73dfe
suservo: support pure-I
2018-05-14 18:48:27 +00:00
0c1caf0744
suservo: clean up and beautify example
2018-05-14 15:22:47 +02:00
504d37b66b
suservo: add SI units functions and document
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m-labs/artiq#788
2018-05-14 12:26:49 +00:00
3027951dd8
integrate new AD9914 driver
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moninj, analyzer, docs, examples, tests.
2018-05-13 23:29:35 +08:00
f055bf88f6
suservo: add clip flags ( #992 )
2018-05-09 07:16:15 +00:00
8812824fb2
suservo: speed up example, interlock mem
2018-04-27 17:17:17 +00:00
5f00326c65
suservo: coeff mem write port READ_FIRST
2018-04-27 15:43:32 +00:00
73fa572275
suservo: documentation, small API changes
2018-04-27 16:53:22 +02:00
fe9834bac4
suservo: update 'technology preview' example [wip]
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Still with mostly undocumented and unstable API.
2018-04-27 12:04:17 +00:00
307cd07b9d
suservo: lots of gateware/ runtime changes
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tested/validated:
* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback
individual changes below:
suservo: correct rtio readback
suservo: example, device_db [wip]
suservo: change rtio channel layout
suservo: mem ports in rio domain
suservo: sck clocked from rio_phy
suservo: cleanup, straighten out timing
suservo: dds cs polarity
suservo: simplify pipeline
suservo: drop unused eem names
suservo: decouple adc SR from IIR
suservo: expand coredevice layer
suservo: start the correct stage
suservo: actually load ctrl
suservo: refactor/tweak adc timing
suservo: implement cpld and dds init
2018-04-27 13:50:26 +02:00
8a1151b54f
suservo: example device db
2018-04-25 17:14:25 +00:00
4fe09fddd5
examples/kc705_nist_clock: update to new ad53xx driver
2018-04-22 15:03:30 +08:00
48b48e44dd
kasli/mitll: fix demo
2018-04-17 20:15:38 +08:00
79f4892e22
kasli/mitll: fix RTIO channel numbers
2018-04-17 20:15:17 +08:00
eac447278f
kasli: add MITLL variant
2018-04-17 19:00:11 +08:00
8d62ea2288
examples: fix KC705 ad53xx
2018-03-25 11:19:54 +08:00
a20dfd9c00
examples/master: ad5360 -> zotino
2018-03-24 16:46:59 +01:00
0505e9124f
kc705: port device_db, ad53xx/zotino example
2018-03-24 16:05:26 +01:00
68e433a3a8
opticlock/device_db: resurrect novogorny
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deleted in a992a67
2018-03-24 13:46:45 +01:00
hartytp
a992a672d9
coredevice/zotino: add ( #969 )
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* Replace ad5360 driver with a ad53xx driver, designed to have a nicer interface
Add Zotino driver and add to opticlock target for Kasli
Test Zotino on hw:
- Verify all timings on the hardware with a scope
- Verify that we can correctly set and read back all registers in a loop (checks for SI and driver issues)
- check we can set LEDs correctly
- check calibration routine + all si unit functions with a good DVM
- look at DAC transitions on a scope (while triggering of a TTL) on persist to check there are no LDAC glitches etc
To do: update examples and e.g. KC705 device db.
2018-03-24 13:41:18 +01:00
