forked from M-Labs/artiq
examples: add Kasli SAWG master
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core_addr = "kasli-1.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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}
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for i in range(8):
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device_db["sawg" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": i*10+0x010006, "parallelism": 4}
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}
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for i in range(8):
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device_db["sawg" + str(8+i)] = {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": i*10+0x020006, "parallelism": 4}
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}
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from artiq.experiment import *
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class SAWGTestDRTIO(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(16)]
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@kernel
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def run(self):
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while True:
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print("waiting for DRTIO ready...")
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while not (self.core.get_drtio_link_status(0) and
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self.core.get_drtio_link_status(1)):
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pass
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print("OK")
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self.core.reset()
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for sawg in self.sawgs:
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delay(1*ms)
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sawg.amplitude1.set(.4)
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# Do not use a sub-multiple of oscilloscope sample rates.
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sawg.frequency0.set(9*MHz)
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while self.core.get_drtio_link_status(0) and self.core.get_drtio_link_status(1):
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pass
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