forked from M-Labs/artiq
kasli_sawgmaster: add Urukul-Sayma example
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from artiq.experiment import *
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class SinesUrukulSayma(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("urukul0_cpld")
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self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
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@kernel
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def run(self):
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# Note: when testing sync, do not reboot Urukul, as it is not
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# synchronized to the FPGA (yet).
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self.core.reset()
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self.urukul0_cpld.init()
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for urukul_ch in self.urukul_chs:
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delay(1*ms)
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urukul_ch.init()
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urukul_ch.set(9*MHz)
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urukul_ch.set_att(6.)
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urukul_ch.sw.on()
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while True:
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print("waiting for DRTIO ready...")
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while not self.core.get_drtio_link_status(0):
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pass
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print("OK")
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self.core.reset()
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for sawg in self.sawgs:
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delay(1*ms)
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sawg.reset()
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for sawg in self.sawgs:
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delay(1*ms)
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sawg.amplitude1.set(.4)
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sawg.frequency0.set(9*MHz)
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while self.core.get_drtio_link_status(0):
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pass
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