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kasli_sawgmaster: add Urukul-Sayma example

This commit is contained in:
Sebastien Bourdeauducq 2018-08-07 17:21:31 +08:00
parent 474bc7b65b
commit 8aa88cfe70
1 changed files with 42 additions and 0 deletions

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from artiq.experiment import *
class SinesUrukulSayma(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("urukul0_cpld")
self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
@kernel
def run(self):
# Note: when testing sync, do not reboot Urukul, as it is not
# synchronized to the FPGA (yet).
self.core.reset()
self.urukul0_cpld.init()
for urukul_ch in self.urukul_chs:
delay(1*ms)
urukul_ch.init()
urukul_ch.set(9*MHz)
urukul_ch.set_att(6.)
urukul_ch.sw.on()
while True:
print("waiting for DRTIO ready...")
while not self.core.get_drtio_link_status(0):
pass
print("OK")
self.core.reset()
for sawg in self.sawgs:
delay(1*ms)
sawg.reset()
for sawg in self.sawgs:
delay(1*ms)
sawg.amplitude1.set(.4)
sawg.frequency0.set(9*MHz)
while self.core.get_drtio_link_status(0):
pass