forked from M-Labs/artiq
kasli: fix SYSU TTL directions
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parent
8aa88cfe70
commit
9ce6233926
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@ -42,7 +42,7 @@ for i in range(40):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut" if i < 4 else "TTLOut",
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"class": "TTLInOut" if i < 16 else "TTLOut",
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"arguments": {"channel": i},
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}
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@ -246,8 +246,10 @@ class SYSU(_StandaloneBase):
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self.rtio_channels = []
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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for i in range(3, 7):
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
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eem.DIO.add_std(self, 3,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
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for i in range(4, 7):
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eem.DIO.add_std(self, i,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X)
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