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kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example

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This commit is contained in:
Sebastien Bourdeauducq 2018-08-06 16:53:13 +08:00
parent bd968211de
commit 65f198bdee
3 changed files with 79 additions and 4 deletions
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71
artiq/examples/kasli_sawgmaster/device_db.py
View File

@ -25,6 +25,77 @@ device_db = {
},
}
for i in range(8):
device_db["ttl" + str(i)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut" if i < 4 else "TTLOut",
"arguments": {"channel": 3+i},
}
device_db.update(
spi_urukul0={
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 11}
},
ttl_urukul0_io_update={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 12}
},
ttl_urukul0_sw0={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 13}
},
ttl_urukul0_sw1={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 14}
},
ttl_urukul0_sw2={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 15}
},
ttl_urukul0_sw3={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 16}
},
urukul0_cpld={
"type": "local",
"module": "artiq.coredevice.urukul",
"class": "CPLD",
"arguments": {
"spi_device": "spi_urukul0",
"io_update_device": "ttl_urukul0_io_update",
"refclk": 150e6,
"clk_sel": 0
}
}
)
for i in range(4):
device_db["urukul0_ch" + str(i)] = {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 26, # 975MHz sample rate
"chip_select": 4 + i,
"cpld_device": "urukul0_cpld",
"sw_device": "ttl_urukul0_sw" + str(i)
}
}
for i in range(8):
device_db["sawg" + str(i)] = {
"type": "local",

2
artiq/examples/kasli_sawgmaster/repository/sines_drtio.py → artiq/examples/kasli_sawgmaster/repository/sines_2sayma.py
View File

@ -1,7 +1,7 @@
from artiq.experiment import *
class SAWGTestDRTIO(EnvExperiment):
class Sines2Sayma(EnvExperiment):
def build(self):
self.setattr_device("core")
self.sawgs = [self.get_device("sawg"+str(i)) for i in range(16)]

10
artiq/gateware/targets/kasli.py
View File

@ -850,7 +850,10 @@ class Master(_MasterBase):
phy = ttl_simple.Output(sc.led)
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))
eem.DIO.add_std(self, 0, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
# matches Tester EEM numbers
eem.DIO.add_std(self, 5,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
eem.Urukul.add_std(self, 1, 0, ttl_serdes_7series.Output_8X)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
@ -863,7 +866,6 @@ class Satellite(_SatelliteBase):
def __init__(self, *args, **kwargs):
_SatelliteBase.__init__(self, *args, **kwargs)
self.rtio_channels = []
phy = ttl_simple.Output(self.platform.request("user_led", 0))
self.submodules += phy
@ -872,7 +874,9 @@ class Satellite(_SatelliteBase):
phy = ttl_simple.Output(self.platform.request("sfp_ctl", i).led)
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))
eem.DIO.add_std(self, 0, ttl_serdes_7series.InOut_8X, ttl_serdes_7series.InOut_8X)
# matches Tester EEM numbers
eem.DIO.add_std(self, 5,
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
self.add_rtio(self.rtio_channels)