forked from M-Labs/artiq
parent
5de2d06568
commit
f50aef1a22
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@ -1,4 +1,4 @@
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core_addr = "10.0.16.119"
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core_addr = "10.0.16.121"
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device_db = {
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"core": {
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@ -135,20 +135,6 @@ device_db = {
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"arguments": {"channel": 15},
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},
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"suservo0": {
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"type": "local",
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"module": "artiq.coredevice.suservo",
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"class": "SUServo",
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"arguments": {
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"channel": 24,
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"pgia_device": "spi_sampler0_pgia",
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"cpld0_device": "urukul0_cpld",
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"cpld1_device": "urukul1_cpld",
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"dds0_device": "urukul0_dds",
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"dds1_device": "urukul1_dds"
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}
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},
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"suservo0_ch0": {
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"type": "local",
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"module": "artiq.coredevice.suservo",
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@ -198,6 +184,20 @@ device_db = {
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"arguments": {"channel": 23, "servo_device": "suservo0"}
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},
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"suservo0": {
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"type": "local",
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"module": "artiq.coredevice.suservo",
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"class": "SUServo",
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"arguments": {
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"channel": 24,
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"pgia_device": "spi_sampler0_pgia",
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"cpld0_device": "urukul0_cpld",
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"cpld1_device": "urukul1_cpld",
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"dds0_device": "urukul0_dds",
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"dds1_device": "urukul1_dds"
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}
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},
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"spi_sampler0_pgia": {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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@ -4,6 +4,8 @@ from migen.genlib.io import DifferentialOutput
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import spi2, grabber
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from artiq.gateware.suservo import servo, pads as servo_pads
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from artiq.gateware.rtio.phy import servo as rtservo
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def _eem_signal(i):
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@ -429,3 +431,79 @@ class Grabber(_EEM):
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phy = ttl_out_cls(pads.p, pads.n)
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy))
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class SUServo(_EEM):
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@staticmethod
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def io(*eems):
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assert len(eems) == 6
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return (Sampler.io(*eems[0:2])
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+ Urukul.io_qspi(*eems[2:4])
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+ Urukul.io_qspi(*eems[4:6]))
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@classmethod
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def add_std(cls, target, eems_sampler, eems_urukul0, eems_urukul1,
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t_rtt=4, clk=1, shift=11, profile=5):
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cls.add_extension(
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target, *(eems_sampler + eems_urukul0 + eems_urukul1))
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eem_sampler = "sampler{}".format(eems_sampler[0])
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eem_urukul0 = "urukul{}".format(eems_urukul0[0])
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eem_urukul1 = "urukul{}".format(eems_urukul1[0])
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sampler_pads = servo_pads.SamplerPads(target.platform, eem_sampler)
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urukul_pads = servo_pads.UrukulPads(
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target.platform, eem_urukul0, eem_urukul1)
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# timings in units of RTIO coarse period
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adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4,
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# account for SCK pipeline latency
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t_conv=57 - 4, t_rtt=t_rtt + 4)
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iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
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accu=48, shift=shift, channel=3,
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profile=profile)
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dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
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channels=adc_p.channels, clk=clk)
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su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
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su = ClockDomainsRenamer("rio_phy")(su)
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target.submodules += sampler_pads, urukul_pads, su
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ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
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target.submodules += ctrls
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target.rtio_channels.extend(
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rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
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mem = rtservo.RTServoMem(iir_p, su)
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target.submodules += mem
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target.rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
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phy = spi2.SPIMaster(
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target.platform.request("{}_pgia_spi_p".format(eem_sampler)),
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target.platform.request("{}_pgia_spi_n".format(eem_sampler)))
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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phy = spi2.SPIMaster(
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target.platform.request("{}_spi_p".format(eem_urukul0)),
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target.platform.request("{}_spi_n".format(eem_urukul0)))
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = target.platform.request("{}_dds_reset".format(eem_urukul0))
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target.specials += DifferentialOutput(0, pads.p, pads.n)
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for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
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pads = target.platform.request("{}_{}".format(eem_urukul0, signal))
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target.specials += DifferentialOutput(
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su.iir.ctrl[i].en_out, pads.p, pads.n)
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phy = spi2.SPIMaster(
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target.platform.request("{}_spi_p".format(eem_urukul1)),
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target.platform.request("{}_spi_n".format(eem_urukul1)))
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = target.platform.request("{}_dds_reset".format(eem_urukul1))
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target.specials += DifferentialOutput(0, pads.p, pads.n)
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for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
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pads = target.platform.request("{}_{}".format(eem_urukul1, signal))
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target.specials += DifferentialOutput(
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su.iir.ctrl[i + 4].en_out, pads.p, pads.n)
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@ -16,9 +16,7 @@ from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import (
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ttl_simple, ttl_serdes_7series, spi2, servo as rtservo)
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from artiq.gateware.suservo import servo, pads as servo_pads
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series
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from artiq.gateware import eem
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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@ -211,67 +209,10 @@ class SUServo(_StandaloneBase):
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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# EEM3, EEM2: Sampler
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self.platform.add_extension(eem.Sampler.io(3, 2))
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sampler_pads = servo_pads.SamplerPads(self.platform, "sampler3")
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# EEM5, EEM4 and EEM7, EEM6: Urukul
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self.platform.add_extension(eem.Urukul.io_qspi(5, 4))
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self.platform.add_extension(eem.Urukul.io_qspi(7, 6))
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urukul_pads = servo_pads.UrukulPads(self.platform,
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"urukul5", "urukul7")
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adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4,
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# account for SCK pipeline latency
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t_conv=57 - 4, t_rtt=4 + 4)
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iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
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accu=48, shift=11, channel=3, profile=5)
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dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
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channels=adc_p.channels, clk=1)
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su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
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su = ClockDomainsRenamer("rio_phy")(su)
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self.submodules += sampler_pads, urukul_pads, su
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ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
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self.submodules += ctrls
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self.rtio_channels.extend(rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
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mem = rtservo.RTServoMem(iir_p, su)
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self.submodules += mem
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self.rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
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# EEM3: Sampler
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phy = spi2.SPIMaster(self.platform.request("sampler3_pgia_spi_p"),
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self.platform.request("sampler3_pgia_spi_n"))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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# EEM5 + EEM4: Urukul
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phy = spi2.SPIMaster(self.platform.request("urukul5_spi_p"),
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self.platform.request("urukul5_spi_n"))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = self.platform.request("urukul5_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
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pads = self.platform.request("urukul5_{}".format(signal))
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self.specials += DifferentialOutput(
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su.iir.ctrl[i].en_out,
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pads.p, pads.n)
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# EEM7 + EEM6: Urukul
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phy = spi2.SPIMaster(self.platform.request("urukul7_spi_p"),
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self.platform.request("urukul7_spi_n"))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = self.platform.request("urukul7_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
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pads = self.platform.request("urukul7_{}".format(signal))
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self.specials += DifferentialOutput(
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su.iir.ctrl[i + 4].en_out,
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pads.p, pads.n)
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# EEM3/2: Sampler, EEM5/4: Urukul, EEM7/6: Urukul
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eem.SUServo.add_std(
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self, eems_sampler=(3, 2),
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eems_urukul0=(5, 4), eems_urukul1=(7, 6))
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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@ -285,12 +226,11 @@ class SUServo(_StandaloneBase):
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self.add_rtio(self.rtio_channels)
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pads = self.platform.lookup_request("sampler3_adc_data_p")
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self.platform.add_false_path_constraints(
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sampler_pads.clkout_p,
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self.rtio_crg.cd_rtio.clk)
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pads.clkout, self.rtio_crg.cd_rtio.clk)
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self.platform.add_false_path_constraints(
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sampler_pads.clkout_p,
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self.crg.cd_sys.clk)
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pads.clkout, self.crg.cd_sys.clk)
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class SYSU(_StandaloneBase):
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