forked from M-Labs/artiq
suservo: coeff mem write port READ_FIRST
This commit is contained in:
parent
73fa572275
commit
5f00326c65
|
@ -95,10 +95,12 @@ class SUServo:
|
|||
def set_config(self, enable):
|
||||
"""Set SU Servo configuration.
|
||||
|
||||
Disabling takes up to 2 Servo cycles (~2.2 µs) to clear
|
||||
the processing pipeline.
|
||||
|
||||
This method advances the timeline by one Servo memory access.
|
||||
|
||||
:param enable: Enable Servo operation. Disabling takes up to 2 Servo
|
||||
cycles (~2.2 µs).
|
||||
:param enable: Enable Servo operation.
|
||||
"""
|
||||
self.write(CONFIG_ADDR, enable)
|
||||
|
||||
|
@ -261,6 +263,10 @@ class Channel:
|
|||
The IIR state is also know as the "integrator", or the DDS amplitude
|
||||
scale factor. It is 18 bits wide and unsigned.
|
||||
|
||||
This method must not be used when the Servo
|
||||
could be writing to the same location. Either deactivate the profile,
|
||||
or deactivate IIR updates, or disable Servo iterations.
|
||||
|
||||
This method advances the timeline by one Servo memory access.
|
||||
|
||||
:param profile: Profile number (0-31)
|
||||
|
|
|
@ -30,11 +30,13 @@ class SUServo(EnvExperiment):
|
|||
self.suservo0.cpld0.set_att_mu(0, 64)
|
||||
delay(1*us)
|
||||
assert self.suservo0.get_status() == 2
|
||||
delay(10*us)
|
||||
|
||||
# set up profile 0 on channel 0
|
||||
self.suservo0_ch0.set_y_mu(0, 0)
|
||||
self.suservo0_ch0.set_iir_mu(
|
||||
profile=0, adc=0, a1=-0x800, b0=0x1000, b1=0, delay=0)
|
||||
delay(10*us)
|
||||
self.suservo0_ch0.set_dds_mu(
|
||||
profile=0, ftw=0x12345667, offset=0x1, pow=0xaa55)
|
||||
# enable channel
|
||||
|
@ -50,6 +52,7 @@ class SUServo(EnvExperiment):
|
|||
|
||||
# check servo status
|
||||
assert self.suservo0.get_status() == 1
|
||||
delay(10*us)
|
||||
|
||||
# reach back ADC data
|
||||
print(self.suservo0.get_adc_mu(0))
|
||||
|
|
|
@ -28,9 +28,11 @@ class RTServoMem(Module):
|
|||
interface."""
|
||||
def __init__(self, w, servo):
|
||||
m_coeff = servo.iir.m_coeff.get_port(write_capable=True,
|
||||
mode=READ_FIRST,
|
||||
we_granularity=w.coeff, clock_domain="rio")
|
||||
assert len(m_coeff.we) == 2
|
||||
m_state = servo.iir.m_state.get_port(write_capable=True,
|
||||
# mode=READ_FIRST,
|
||||
clock_domain="rio")
|
||||
self.specials += m_state, m_coeff
|
||||
|
||||
|
|
|
@ -344,7 +344,7 @@ class IIR(Module):
|
|||
]
|
||||
|
||||
m_coeff = self.m_coeff.get_port()
|
||||
m_state = self.m_state.get_port(write_capable=True)
|
||||
m_state = self.m_state.get_port(write_capable=True) # mode=READ_FIRST
|
||||
self.specials += m_state, m_coeff
|
||||
|
||||
dsp = DSP(w)
|
||||
|
|
Loading…
Reference in New Issue