forked from M-Labs/artiq
test: add Urukul CPLD HITL tests
for #1143 Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -61,7 +61,7 @@ def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
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(io_update << CFG_IO_UPDATE) |
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(mask_nu << CFG_MASK_NU) |
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((clk_sel & 0x01) << CFG_CLK_SEL0) |
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((clk_sel & 0x02) << (CFG_CLK_SEL1-1)) |
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((clk_sel & 0x02) << (CFG_CLK_SEL1 - 1)) |
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(sync_sel << CFG_SYNC_SEL) |
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(rst << CFG_RST) |
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(io_rst << CFG_IO_RST))
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@ -342,4 +342,9 @@ device_db.update(
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loop_out="ttl4",
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loop_in="ttl0",
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# Urukul CPLD with sync and io_update, IFC MODE 0b1000
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urukul_cpld="urukul0_cpld",
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# Urukul AD9910 with switch TTL, internal 125 MHz MMCX connection
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urukul_ad9910="urukul0_ch0",
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)
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@ -0,0 +1,147 @@
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import unittest
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from artiq.experiment import *
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from artiq.test.hardware_testbench import ExperimentCase
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from artiq.coredevice import urukul
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class UrukulExp(EnvExperiment):
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def build(self, runner):
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self.setattr_device("core")
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self.dev = self.get_device("urukul_cpld")
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self.runner = runner
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def run(self):
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getattr(self, self.runner)()
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@kernel
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def instantiate(self):
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pass
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@kernel
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def init(self):
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self.core.break_realtime()
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self.dev.init()
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@kernel
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def cfg_write(self):
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self.core.break_realtime()
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self.dev.init()
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self.dev.cfg_write(self.dev.cfg_reg)
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@kernel
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def sta_read(self):
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self.core.break_realtime()
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self.dev.init()
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sta = self.dev.sta_read()
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self.set_dataset("sta", sta)
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@kernel
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def switches(self):
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self.core.break_realtime()
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self.dev.init()
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self.dev.io_rst()
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self.dev.cfg_sw(0, 0)
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self.dev.cfg_sw(0, 1)
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self.dev.cfg_sw(3, 1)
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self.dev.cfg_switches(0b1010)
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@kernel
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def switch_speed(self):
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self.core.break_realtime()
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self.dev.init()
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n = 10
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t0 = self.core.get_rtio_counter_mu()
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for i in range(n):
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self.dev.cfg_sw(3, i & 1)
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self.set_dataset("dt", self.core.mu_to_seconds(
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self.core.get_rtio_counter_mu() - t0)/n)
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@kernel
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def switches_readback(self):
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self.core.reset() # clear switch TTLs
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self.dev.init()
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sw_set = 0b1010
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self.dev.cfg_switches(sw_set)
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sta_get = self.dev.sta_read()
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self.set_dataset("sw_set", sw_set)
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self.set_dataset("sta_get", sta_get)
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@kernel
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def att(self):
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self.core.break_realtime()
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self.dev.init()
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att_set = 0x12345678
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self.dev.set_all_att_mu(att_set)
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att_get = self.dev.get_att_mu()
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self.set_dataset("att_set", att_set)
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self.set_dataset("att_get", att_get)
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@kernel
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def att_speed(self):
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self.core.break_realtime()
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self.dev.init()
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n = 10
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t0 = self.core.get_rtio_counter_mu()
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for i in range(n):
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self.dev.set_att(3, 30*dB)
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self.set_dataset("dt", self.core.mu_to_seconds(
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self.core.get_rtio_counter_mu() - t0)/n)
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@kernel
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def io_update(self):
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self.core.break_realtime()
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self.dev.init()
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self.dev.io_update.pulse_mu(8)
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@kernel
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def sync(self):
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self.core.break_realtime()
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self.dev.init()
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self.dev.set_sync_div(2)
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class UrukulTest(ExperimentCase):
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def test_instantiate(self):
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self.execute(UrukulExp, "instantiate")
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def test_init(self):
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self.execute(UrukulExp, "init")
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def test_cfg_write(self):
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self.execute(UrukulExp, "cfg_write")
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def test_sta_read(self):
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self.execute(UrukulExp, "sta_read")
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sta = self.dataset_mgr.get("sta")
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print(hex(sta))
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self.assertEqual(urukul.urukul_sta_ifc_mode(sta), 0b0001)
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def test_switches(self):
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self.execute(UrukulExp, "switches")
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def test_switch_speed(self):
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self.execute(UrukulExp, "switch_speed")
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self.assertLess(self.dataset_mgr.get("dt"), 3*us)
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def test_switches_readback(self):
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self.execute(UrukulExp, "switches_readback")
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sw_get = urukul.urukul_sta_rf_sw(self.dataset_mgr.get("sta_get"))
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sw_set = self.dataset_mgr.get("sw_set")
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self.assertEqual(sw_get, sw_set)
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def test_att(self):
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self.execute(UrukulExp, "att")
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att_set = self.dataset_mgr.get("att_set")
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att_get = self.dataset_mgr.get("att_get")
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self.assertEqual(att_set, att_get)
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def test_att_speed(self):
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self.execute(UrukulExp, "att_speed")
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self.assertLess(self.dataset_mgr.get("dt"), 3*us)
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def test_io_update(self):
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self.execute(UrukulExp, "io_update")
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def test_sync(self):
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self.execute(UrukulExp, "sync")
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