forked from M-Labs/artiq
examples: add Sayma VHDCI DIO
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core_addr = "sayma-1.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"core_dma": {
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"type": "local",
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"module": "artiq.coredevice.dma",
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"class": "CoreDMA"
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},
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"fmcdio_dirctl_clk": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 6}
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},
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"fmcdio_dirctl_ser": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 7}
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},
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"fmcdio_dirctl_latch": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 8}
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},
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"fmcdio_dirctl": {
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"type": "local",
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"module": "artiq.coredevice.shiftreg",
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"class": "ShiftReg",
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"arguments": {"clk": "fmcdio_dirctl_clk",
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"ser": "fmcdio_dirctl_ser",
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"latch": "fmcdio_dirctl_latch"}
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},
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}
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for i in range(8):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 9+i},
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}
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from artiq.experiment import *
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from artiq.coredevice.fmcdio_vhdci_eem import *
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class Demo(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("fmcdio_dirctl")
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self.ttls = [self.get_device("ttl" + str(i)) for i in range(8)]
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self.dirctl_word = (
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shiftreg_bits(2, dio_bank0_out_pins) |
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shiftreg_bits(2, dio_bank1_out_pins))
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@kernel
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def run(self):
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self.core.reset()
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delay(10*ms)
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self.fmcdio_dirctl.set(self.dirctl_word)
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delay(10*ms)
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while True:
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for ttl in self.ttls:
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ttl.pulse(1*ms)
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