hartytp
a058be2ede
wrpll: fix test_helper_collector
2020-10-08 19:43:12 +08:00
d0d0a02fd0
test: added lit test for new error messages
2020-10-08 19:38:26 +08:00
e9988f9d3b
compiler: error message for custom operations
...
Emit error messages for custom comparison and inclusion test,
instead of compiler crashing.
2020-10-08 19:38:26 +08:00
db62cf2abe
wrpll: convert tests to self-checking unittests
2020-10-08 18:38:01 +08:00
07d43b6e5f
wrpll: babysit Vivado DSP retiming
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Design now passes timing.
2020-10-08 17:51:27 +08:00
7dfb4af682
kasli2: work around vivado clock constraint problem
2020-10-08 16:31:39 +08:00
96a5df0dc6
kasli2: add false path constraint for wrpll helper clock
2020-10-08 16:19:44 +08:00
6248970ef8
wrpll: clean up matlab comparison test
2020-10-08 15:40:15 +08:00
hartytp
cd8c2ce713
wrpll: add test to compare collector+filter against Matlab simulation
2020-10-08 15:36:56 +08:00
hartytp
d780faf4ac
wrpll.si549: initialize the clock divider to a sensible value
2020-10-08 15:32:27 +08:00
hartytp
e6ff2ddc32
wrpll: add more diagnostics in firmware and adapt to recent gateware changes
2020-10-08 15:32:27 +08:00
hartytp
7d7be6e711
wrpll.core: move collector into helper CD so we can get tags out while the filters are reset
2020-10-08 15:32:27 +08:00
3fa5d0b963
wrpll: clean up sign extension
2020-10-08 15:32:27 +08:00
hartytp
87911810d6
wrpll.core: add CSRs to monitor the collector outputs
2020-10-08 15:32:27 +08:00
hartytp
f2f942a8b4
wrpll.ddmtd: remove CSRs from DDMTD
...
We will gather then from the collector output so we can get all tags on the same cycle
2020-10-08 15:32:27 +08:00
hartytp
85bb641917
wrpll.ddmtd: fix first edge deglitcher
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The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
2020-10-08 15:32:27 +08:00
hartytp
f3cd0fc675
wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit.
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TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
2020-10-08 15:32:27 +08:00
hartytp
e5e648bde1
wrpll: add bit shift for collector helper output
2020-10-08 15:32:27 +08:00
hartytp
c9ae406ac6
wrpll: change the DDMTD helper frequency to match CERN, improve docs
2020-10-08 15:32:27 +08:00
hartytp
f6f6045f1a
wrpll.thls: fix make
2020-10-08 15:32:27 +08:00
hartytp
b44b870452
wrpll.filters: update to match Weida's MatLab simulations
2020-10-08 15:32:27 +08:00
hartytp
e9ab434fa7
wrpll.core: update for modified collector
2020-10-08 15:32:27 +08:00
17c952b8fb
wrpll: style
2020-10-08 15:32:27 +08:00
hartytp
ebb7ccbfd1
wrpll: document DDMTD collector and fix unwrapping
2020-10-08 15:32:27 +08:00
7c2519c912
manual: nixpkgs 20.09
2020-10-08 09:18:46 +08:00
1bfe977203
manual: sphinx mock module whack-a-mole
2020-10-07 19:25:26 +08:00
66401aee9c
dashboard: cleanup import
2020-10-07 19:24:54 +08:00
6baf3b2198
RELEASE_NOTES: fix indentation
2020-10-07 19:24:34 +08:00
fe6115bcbb
compiler: fix incorrect with behavior
2020-10-07 18:59:35 +08:00
02f46e8b79
Fixes none to bool coercion
...
Fixes #1413 and #1414 .
2020-10-07 15:34:24 +08:00
88d346fa26
fixes with statement with multiple items
...
Closes #1478
2020-10-07 15:33:34 +08:00
9214e0f3e2
firmware: fix Si5324 CKIN selection on Kasli 2.0
...
https://github.com/sinara-hw/Kasli/issues/82#issuecomment-702129805
2020-10-02 20:35:32 +08:00
eecd97ce4c
phaser: debug and comments
2020-09-27 17:15:16 +00:00
c453c24fb0
phaser: tweak slacks
2020-09-26 21:16:08 +00:00
6c8bddcf8d
phaser: tune sync_dly
2020-09-26 21:13:00 +00:00
569e5e56cd
phaser: autotune and fix fifo_offset
2020-09-26 20:37:16 +00:00
2fba3cfc78
phaser: debug init, systematic bring-up
2020-09-25 20:54:59 +00:00
fec2f8b763
phaser: increase slack for iotest
2020-09-24 10:59:22 +00:00
a65239957f
ad53xx: distinguish errors
2020-09-24 10:52:03 +02:00
6e6480ec21
phaser: tweak slacks and errors, identify trf
2020-09-24 08:38:30 +00:00
03d5f985f8
phaser: another artiq-python signed integer quirk
2020-09-23 15:40:54 +00:00
ef65ee18bd
dac34h84: unflip spectrum, clear nco
2020-09-23 08:35:56 +00:00
50b4eb4840
Merge branch 'master' into phaser
...
* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
...
2020-09-22 16:02:25 +00:00
c55f2222dc
fastino: documentation and eem pass-through
...
* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
ad096f294c
phaser: add hitl test exercising the complete API
2020-09-22 15:35:19 +00:00
85d16e3e5f
phaser: tweaks
2020-09-22 15:27:38 +00:00
5c76f5c319
tester: add phaser
2020-09-22 14:36:49 +00:00
fd5e221898
phaser: dac and trf register maps, init code
2020-09-22 14:08:39 +00:00
3e036e365a
phaser: nco, settings and init tweaks
2020-09-22 09:52:49 +00:00
fdb2867757
phaser: fewer iotest patterns
2020-09-21 17:06:26 +02:00
