forked from M-Labs/artiq
phaser: tweak slacks
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@ -177,14 +177,14 @@ class Phaser:
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board_id = self.read8(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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raise ValueError("invalid board id")
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delay(20*us) # slack
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delay(.1*ms) # slack
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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delay(20*us) # slack
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delay(.1*ms) # slack
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is_baseband = hw_rev & PHASER_HW_REV_VARIANT
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gw_rev = self.read8(PHASER_ADDR_GW_REV)
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delay(20*us) # slack
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delay(.1*ms) # slack
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# allow a few errors during startup and alignment since boot
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if self.get_crc_err() > 20:
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@ -218,13 +218,13 @@ class Phaser:
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delay(.1*ms)
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t = self.get_dac_temperature()
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delay(.5*ms)
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delay(.1*ms)
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if t < 10 or t > 90:
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raise ValueError("DAC temperature out of bounds")
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for data in self.dac_mmap:
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self.dac_write(data >> 16, data)
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delay(20*us)
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delay(40*us)
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# pll_ndivsync_ena disable
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config18 = self.dac_read(0x18)
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