forked from M-Labs/artiq
phaser: tweak slacks and errors, identify trf
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03d5f985f8
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@ -167,11 +167,11 @@ class Phaser:
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delay(20*us) # slack
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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delay(.1*ms) # slack
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delay(20*us) # slack
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is_baseband = hw_rev & PHASER_HW_REV_VARIANT
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gw_rev = self.read8(PHASER_ADDR_GW_REV)
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delay(.1*ms) # slack
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delay(20*us) # slack
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# allow a few errors during startup and alignment since boot
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if self.get_crc_err() > 20:
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@ -185,11 +185,11 @@ class Phaser:
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self.set_fan_mu(0)
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# bring everything out of reset, keep tx off
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self.set_cfg(clk_sel=self.clk_sel, dac_txena=0)
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delay(.1*ms) # slack
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# TODO: crossing dac_clk (125 MHz) edges with sync_dly (0-7 ns)
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# should change the optimal fifo_offset by 4
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self.set_sync_dly(4)
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delay(.1*ms) # slack
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# 4 wire SPI, sif4_enable
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self.dac_write(0x02, 0x0080)
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@ -207,7 +207,7 @@ class Phaser:
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for data in self.dac_mmap:
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self.dac_write(data >> 16, data)
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delay(.1*ms)
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delay(20*us)
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patterns = [
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[0xf05a, 0x05af, 0x5af0, 0xaf05], # test channel/iq/byte/nibble
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@ -219,16 +219,16 @@ class Phaser:
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# either side) and no need to tune at runtime.
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# Parity provides another level of safety.
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for i in range(len(patterns)):
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delay(.5*ms)
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delay(.2*ms)
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errors = self.dac_iotest(patterns[i])
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if errors:
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raise ValueError("DAC iotest failure")
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delay(10*ms) # let it settle
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delay(2*ms) # let it settle
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lvolt = self.dac_read(0x18) & 7
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delay(.1*ms)
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if lvolt < 2 or lvolt > 5:
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raise ValueError("DAC PLL tuning voltage out of bounds")
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raise ValueError("DAC PLL lock failed, check clocking")
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# self.dac_write(0x20, 0x0000) # stop fifo sync
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# alarm = self.get_sta() & 1
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@ -270,15 +270,24 @@ class Phaser:
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abs(data_i - data_q) > 2):
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raise ValueError("DUC+oscillator phase/amplitude test failed")
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if not is_baseband:
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for data in channel.trf_mmap:
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channel.trf_write(data)
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delay(.1*ms)
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delay(1*ms) # lock
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lock_detect = self.get_sta() & (PHASER_STA_TRF0_LD << ch)
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delay(.1*ms)
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if not lock_detect:
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raise ValueError("TRF quadrature upconverter lock failure")
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if is_baseband:
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continue
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if channel.trf_read(0) & 0x7f != 0x68:
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raise ValueError("TRF identification failed")
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delay(.1*ms)
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delay(.2*ms)
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for data in channel.trf_mmap:
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channel.trf_write(data)
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delay(2*ms) # lock
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if not (self.get_sta() & (PHASER_STA_TRF0_LD << ch)):
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raise ValueError("TRF lock failure")
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delay(.1*ms)
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if channel.trf_read(0) & 0x1000:
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raise ValueError("TRF R_SAT_ERR")
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delay(.1*ms)
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self.set_cfg(clk_sel=self.clk_sel) # txena
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@ -799,7 +808,8 @@ class PhaserChannel:
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self.phaser.spi_cfg(select=0, div=34, end=1, length=1)
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self.phaser.spi_write(0)
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delay((1 + 1)*34*4*ns)
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return self.trf_write(0x00000008, readback=True)
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return self.trf_write(0x00000008 | (cnt_mux_sel << 27),
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readback=True)
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class PhaserOscillator:
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@ -37,7 +37,7 @@ class TRF372017:
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ld_ana_prec = 0 # 2b
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cp_tristate = 0 # 2b
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speedup = 0
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ld_dig_prec = 0
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ld_dig_prec = 1
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en_dith = 1
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mod_ord = 2 # 3rd order, 2b
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dith_sel = 0
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