forked from M-Labs/artiq
phaser: fewer iotest patterns
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@ -173,11 +173,9 @@ class Phaser:
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delay(.5*ms)
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patterns = [
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[0xffff, 0xffff, 0x0000, 0x0000], # test channel
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[0xaa55, 0x55aa, 0x55aa, 0xaa5a], # test iq
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[0xaa55, 0xaa55, 0x55aa, 0x55aa], # test byte
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[0x7a7a, 0xb6b6, 0xeaea, 0x4545], # ds pattern a
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[0x1a1a, 0x1616, 0xaaaa, 0xc6c6], # ds pattern b
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[0xf05a, 0x05af, 0x5af0, 0xaf05], # test channel/iq/byte/nibble
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[0x7a7a, 0xb6b6, 0xeaea, 0x4545], # datasheet pattern a
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[0x1a1a, 0x1616, 0xaaaa, 0xc6c6], # datasheet pattern b
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]
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# A data delay of 2*50 ps heuristically and reproducibly matches
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# FPGA+board+DAC skews. There is plenty of margin (>= 250 ps
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