forked from M-Labs/artiq
phaser: autotune and fix fifo_offset
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@ -115,10 +115,20 @@ class Phaser:
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class and applied during `init()`. See the :class:`DAC34H84` and
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:class:`TRF372017` source for details.
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.. note:: To establish deterministic latency between RTIO time base and DAC
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output, the DAC FIFO read pointer value (`fifo_offset`) must be
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fixed. If `tune_fifo_offset=True` (the default) a value with maximum
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margin is determined automatically by `dac_tune_fifo_offset` each time
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`init()` is called. This value should be used for the `fifo_offset` key
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of the `dac` settings of Phaser in `device_db.py` and automatic
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tuning should be disabled by `tune_fifo_offset=False`.
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:param channel: Base RTIO channel number
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:param core_device: Core device name (default: "core")
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:param miso_delay: Fastlink MISO signal delay to account for cable
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and buffer round trip. Tuning this might be automated later.
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:param tune_fifo_offset: Tune the DAC FIFO read pointer offset
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(default=True)
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:param clk_sel: Select the external SMA clock input (1 or 0)
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:param dac: DAC34H84 DAC settings as a dictionary.
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:param trf0: Channel 0 TRF372017 quadrature upconverter settings as a
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@ -135,8 +145,8 @@ class Phaser:
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kernel_invariants = {"core", "channel_base", "t_frame", "miso_delay",
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"dac_mmap"}
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def __init__(self, dmgr, channel_base, miso_delay=1, clk_sel=0,
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dac=None, trf0=None, trf1=None, core_device="core"):
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def __init__(self, dmgr, channel_base, miso_delay=1, tune_fifo_offset=True,
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clk_sel=0, dac=None, trf0=None, trf1=None, core_device="core"):
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self.channel_base = channel_base
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self.core = dmgr.get(core_device)
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# TODO: auto-align miso-delay in phy
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@ -146,6 +156,7 @@ class Phaser:
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assert self.core.ref_period == 1*ns
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self.t_frame = 10*8*4
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self.clk_sel = clk_sel
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self.tune_fifo_offset = tune_fifo_offset
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self.dac_mmap = DAC34H84(dac).get_mmap()
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@ -232,6 +243,9 @@ class Phaser:
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if lvolt < 2 or lvolt > 5:
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raise ValueError("DAC PLL lock failed, check clocking")
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if self.tune_fifo_offset:
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self.dac_tune_fifo_offset()
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# self.dac_write(0x20, 0x0000) # stop fifo sync
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# alarm = self.get_sta() & 1
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# delay(.1*ms)
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@ -578,6 +592,49 @@ class Phaser:
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self.dac_write(0x04, 0x0000) # clear iotest_result
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return errors
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@kernel
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def dac_tune_fifo_offset(self):
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"""Scan through `fifo_offset` and configure midpoint setting.
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:return: Optimal `fifo_offset` setting with maximum margin to write
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pointer.
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"""
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# expect two or three error free offsets:
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#
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# read offset 01234567
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# write pointer w
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# distance 32101234
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# error free x xx
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config9 = self.dac_read(0x09)
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delay(.1*ms)
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good = 0
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for o in range(8):
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# set new fifo_offset
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self.dac_write(0x09, (config9 & 0x1fff) | (o << 13))
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self.clear_dac_alarms()
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delay(.1*ms) # run
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alarms = self.get_dac_alarms()
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delay(.1*ms) # slack
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if (alarms >> 11) & 0x7 == 0: # any fifo alarm
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good |= 1 << o
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# if there are good offsets accross the wrap around
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# offset for computations
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if good & 0x81 == 0x81:
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good = ((good << 4) & 0xf0) | (good >> 4)
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offset = 4
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else:
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offset = 0
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# calculate mean
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sum = 0
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count = 0
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for o in range(8):
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if good & (1 << o):
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sum += o
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count += 1
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best = ((sum // count) + offset) % 8
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self.dac_write(0x09, (config9 & 0x1fff) | (best << 13))
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return best
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class PhaserChannel:
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"""Phaser channel IQ pair.
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