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synced 2024-12-25 11:18:27 +08:00
wrpll: new frequency meter
As per Mattermost discussion with Tom.
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commit
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@ -264,12 +264,25 @@ mod si549 {
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}
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}
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fn get_helper_frequency() -> u32 {
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unsafe { csr::wrpll::helper_frequency_start_write(1); }
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clock::spin_us(10_000);
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unsafe { csr::wrpll::helper_frequency_stop_write(1); }
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clock::spin_us(1);
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unsafe { csr::wrpll::helper_frequency_counter_read() }
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fn get_frequencies() -> (u32, u32, u32) {
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unsafe {
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csr::wrpll::frequency_counter_update_en_write(1);
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clock::spin_us(200_000); // wait for at least one update
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csr::wrpll::frequency_counter_update_en_write(0);
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clock::spin_us(1);
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let helper = csr::wrpll::frequency_counter_counter_helper_read();
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let main = csr::wrpll::frequency_counter_counter_rtio_read();
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let cdr = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
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(helper, main, cdr)
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}
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}
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fn log_frequencies() {
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let (f_helper, f_main, f_cdr) = get_frequencies();
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let conv_khz = |f| 4*(f as u64)*(csr::CONFIG_CLOCK_FREQUENCY as u64)/(1000*(1 << 23));
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info!("helper clock frequency: {}kHz ({})", conv_khz(f_helper), f_helper);
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info!("main clock frequency: {}kHz ({})", conv_khz(f_main), f_main);
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info!("CDR clock frequency: {}kHz ({})", conv_khz(f_cdr), f_cdr);
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}
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fn get_ddmtd_main_tag() -> u16 {
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@ -309,7 +322,7 @@ pub fn init() {
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unsafe { csr::wrpll::helper_reset_write(0); }
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clock::spin_us(1);
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info!("helper clock frequency: {}MHz", get_helper_frequency()/10000);
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log_frequencies();
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let mut tags = [0; 10];
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for i in 0..tags.len() {
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tags[i] = get_ddmtd_main_tag();
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@ -319,6 +332,7 @@ pub fn init() {
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pub fn select_recovered_clock(rc: bool) {
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info!("select_recovered_clock: {}", rc);
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log_frequencies();
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if rc {
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let mut tags = [0; 10];
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for i in 0..tags.len() {
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@ -9,32 +9,43 @@ from artiq.gateware.drtio.wrpll import thls, filters
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class FrequencyCounter(Module, AutoCSR):
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def __init__(self):
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self.counter = CSRStatus(32)
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self.start = CSR()
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self.stop = CSR()
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def __init__(self, timer_width=23, counter_width=23, domains=["helper", "rtio", "rtio_rx0"]):
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for domain in domains:
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name = "counter_" + domain
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counter = CSRStatus(counter_width, name=name)
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setattr(self, name, counter)
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self.update_en = CSRStorage()
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ps_start = PulseSynchronizer("sys", "helper")
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ps_stop = PulseSynchronizer("sys", "helper")
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self.submodules += ps_start, ps_stop
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timer = Signal(timer_width)
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timer_tick = Signal()
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self.sync += Cat(timer, timer_tick).eq(timer + 1)
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self.comb += [
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ps_start.i.eq(self.start.re & self.start.r),
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ps_stop.i.eq(self.stop.re & self.stop.r)
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]
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for domain in domains:
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sync_domain = getattr(self.sync, domain)
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divider = Signal(2)
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sync_domain += divider.eq(divider + 1)
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counter = Signal(32)
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self.specials += MultiReg(counter, self.counter.status)
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divided = Signal()
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divided.attr.add("no_retiming")
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sync_domain += divided.eq(divider[-1])
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divided_sys = Signal()
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self.specials += MultiReg(divided, divided_sys)
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counting = Signal()
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self.sync.helper += [
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If(counting, counter.eq(counter + 1)),
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If(ps_start.o,
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counter.eq(0),
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counting.eq(1)
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),
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If(ps_stop.o, counting.eq(0))
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]
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divided_sys_r = Signal()
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divided_tick = Signal()
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self.sync += divided_sys_r.eq(divided_sys)
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self.comb += divided_tick.eq(divided_sys & ~divided_sys_r)
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counter = Signal(counter_width)
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counter_csr = getattr(self, "counter_" + domain)
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self.sync += [
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If(timer_tick,
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If(self.update_en.storage, counter_csr.status.eq(counter)),
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counter.eq(0),
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).Else(
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If(divided_tick, counter.eq(counter + 1))
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)
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]
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class WRPLL(Module, AutoCSR):
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@ -52,7 +63,8 @@ class WRPLL(Module, AutoCSR):
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self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
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self.submodules.main_dcxo = Si549(main_dcxo_i2c)
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self.submodules.helper_frequency = FrequencyCounter() # for diagnostics
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# for diagnostics and PLL initialization
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self.submodules.frequency_counter = FrequencyCounter()
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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