mirror of https://github.com/m-labs/artiq
fastino: add [WIP]
parent
8f9948a1ff
commit
2c4e5bfee4
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@ -0,0 +1,124 @@
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"""RTIO driver for the Fastino 32channel, 16 bit, 2.5 MS/s per channel,
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streaming DAC.
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TODO: Example, describe update/hold
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"""
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from artiq.language.core import kernel, portable
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.language.units import us
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class Fastino:
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"""Fastino 32-channel, 16-bit, 2.5 MS/s per channel streaming DAC
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:param channel: RTIO channel number
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:param core_device: Core device name (default: "core")
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"""
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kernel_invariants = {"core", "channel"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.channel = channel << 8
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self.core = dmgr.get(core_device)
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@kernel
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def init(self):
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"""Initialize the device.
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This clears reset, unsets DAC_CLR, enables AFE_PWR,
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clears error counters, then enables error counting
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"""
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self.set_cfg(0x8)
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delay(1*us)
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self.set_cfg(0x0)
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delay(1*us)
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@kernel
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def write(self, addr, data):
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"""Write data to a Fastino register.
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:param addr: Address to write to.
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:param data: Data to write.
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"""
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rtio_output(self.channel | addr, data)
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@kernel
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def read(self, addr):
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"""Read from Fastino register.
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TODO: untested
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:param addr: Address to read from.
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:return: The data read.
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"""
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rtio_output(self.channel | addr | 0x80)
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return rtio_input_data(self.channel >> 8)
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@kernel
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def set_dac_mu(self, dac, data):
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"""Write DAC data in machine units.
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:param dac: DAC channel to write to (0-31).
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:param data: DAC word to write, 16 bit unsigned integer, in machine
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units.
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"""
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self.write(dac, data)
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@portable
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def voltage_to_mu(self, voltage):
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"""Convert SI Volts to DAC machine units.
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:param voltage: Voltage in SI Volts.
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:return: DAC data word in machine units, 16 bit integer.
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"""
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return int(round((0x8000/10.)*voltage)) + 0x8000
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@kernel
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def set_dac(self, dac, voltage):
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"""Set DAC data to given voltage.
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:param dac: DAC channel (0-31).
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:param voltage: Desired output voltage.
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"""
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self.write(dac, self.voltage_to_mu(voltage))
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@kernel
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def update(self, update):
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"""Schedule channels for update.
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:param update: Bit mask of channels to update (32 bit).
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"""
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self.write(0x20, update)
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@kernel
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def set_hold(self, hold):
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"""Set channels to manual update.
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:param hold: Bit mask of channels to hold (32 bit).
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"""
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self.write(0x21, hold)
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@kernel
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def set_cfg(self, reset=0, afe_power_down=0, dac_clr=0, clr_err=0):
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"""Set configuration bits.
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:param reset: Reset SPI PLL and SPI clock domain.
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:param afe_power_down: Disable AFE power.
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:param dac_clr: Assert all 32 DAC_CLR signals setting all DACs to
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mid-scale (0 V).
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:param clr_err: Clear error counters and PLL reset indicator.
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This clears the sticky red error LED. Must be cleared to enable
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error counting.
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"""
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self.write(0x22, (reset << 0) | (afe_pwr_disable << 1) |
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(dac_clr << 2) | (clr_err << 3))
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@kernel
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def set_leds(self, leds):
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"""Set the green user-defined LEDs
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:param leds: LED status, 8 bit integer each bit corresponding to one
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green LED.
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"""
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self.write(0x23, leds)
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@ -473,6 +473,18 @@ class PeripheralManager:
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channel=rtio_offset)
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return 2
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def process_fastino(self, rtio_offset, peripheral):
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self.gen("""
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device_db["{name}"] = {{
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"type": "local",
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"module": "artiq.coredevice.fastino",
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"class": "Fastino",
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"arguments": {{"channel": 0x{channel:06x}}}
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}}""",
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name=self.get_name("fastino"),
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channel=rtio_offset)
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return 1
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def process(self, rtio_offset, peripheral):
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processor = getattr(self, "process_"+str(peripheral["type"]))
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return processor(rtio_offset, peripheral)
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@ -5,7 +5,7 @@ from migen.genlib.io import DifferentialOutput
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import spi2, ad53xx_monitor, grabber
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from artiq.gateware.suservo import servo, pads as servo_pads
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from artiq.gateware.rtio.phy import servo as rtservo
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from artiq.gateware.rtio.phy import servo as rtservo, fastino
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def _eem_signal(i):
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@ -603,3 +603,25 @@ class Mirny(_EEM):
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phy = ttl_out_cls(pads.p, pads.n)
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy))
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class Fastino(_EEM):
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@staticmethod
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def io(eem, iostandard="LVDS_25"):
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return [
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("fastino{}_ser_{}".format(eem, pol), 0,
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Subsignal("clk", Pins(_eem_pin(eem, 0, pol))),
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Subsignal("mosi", Pins(*(_eem_pin(eem, i, pol)
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for i in range(1, 7)))),
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Subsignal("miso", Pins(_eem_pin(eem, 7, pol))),
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IOStandard(iostandard),
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) for pol in "pn"]
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@classmethod
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def add_std(cls, target, eem, iostandard="LVDS_25"):
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cls.add_extension(target, eem, iostandard=iostandard)
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phy = fastino.Fastino(target.platform.request("fastino{}_ser_p".format(eem)),
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target.platform.request("fastino{}_ser_n".format(eem)))
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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@ -0,0 +1,199 @@
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.io import DifferentialOutput, DifferentialInput, DDROutput
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from artiq.gateware.rtio import rtlink
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class SerDes(Module):
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def transpose(self, i, n):
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# i is n,m c-contiguous
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# o is m,n c-contiguous
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m = len(i)//n
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assert n*m == len(i)
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def __init__(self, pins, pins_n):
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n_bits = 16 # bits per dac data word
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n_channels = 32 # channels per fastino
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n_div = 7 # bits per lane and word
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assert n_div == 7
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n_frame = 14 # word per frame
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n_lanes = len(pins.mosi) # number of data lanes
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n_checksum = 12 # checksum bits
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n_addr = 4 # readback address bits
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n_word = n_lanes*n_div
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n_body = n_word*n_frame - (n_frame//2 + 1) - n_checksum
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# dac data words
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self.dacs = [Signal(n_bits) for i in range(n_channels)]
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# dac update enable
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self.enable = Signal(n_channels)
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# configuration word
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self.cfg = Signal(20)
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# readback data
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self.dat_r = Signal(n_frame//2*(1 << n_addr))
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# data load synchronization event
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self.stb = Signal()
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# # #
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# crc-12 telco
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self.submodules.crc = LiteEthMACCRCEngine(
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data_width=2*n_lanes, width=n_checksum, polynom=0x80f)
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addr = Signal(4)
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body_ = Cat(self.cfg, addr, self.enable, self.dacs)
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assert len(body_) == n_body
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body = Signal(n_body)
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self.comb += body.eq(body_)
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words_ = []
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j = 0
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for i in range(n_frame): # iterate over words
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if i == 0: # data and checksum
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k = n_word - n_checksum
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elif i == 1: # marker
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words_.append(C(1))
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k = n_word - 1
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elif i < n_frame//2 + 2: # marker
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words_.append(C(0))
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k = n_word - 1
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else: # full word
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k = n_word
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# append corresponding frame body bits
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words_.append(body[j:j + k])
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j += k
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words_ = Cat(words_)
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assert len(words_) == n_frame*n_word - n_checksum
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words = Signal(len(words_))
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self.comb += words.eq(words_)
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clk = Signal(n_div, reset=0b1100011)
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clk_stb = Signal()
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i_frame = Signal(max=n_div*n_frame//2) # DDR
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frame_stb = Signal()
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sr = [Signal(n_frame*n_div - n_checksum//n_lanes, reset_less=True)
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for i in range(n_lanes)]
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assert len(Cat(sr)) == len(words)
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# DDR bits for each register
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ddr_data = Cat([sri[-2] for sri in sr], [sri[-1] for sri in sr])
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self.comb += [
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# assert one cycle ahead
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clk_stb.eq(~clk[0] & clk[-1]),
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# double period because of DDR
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frame_stb.eq(i_frame == n_div*n_frame//2 - 1),
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# LiteETHMACCRCEngine takes data LSB first
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self.crc.data[::-1].eq(ddr_data),
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self.stb.eq(frame_stb & clk_stb),
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]
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miso = Signal()
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miso_sr = Signal(n_frame, reset_less=True)
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self.sync.rio_phy += [
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# shift 7 bit clock pattern by two bits each DDR cycle
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clk.eq(Cat(clk[-2:], clk)),
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[sri[2:].eq(sri) for sri in sr],
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self.crc.last.eq(self.crc.next),
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If(clk[:2] == 0, # TODO: tweak MISO sampling
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miso_sr.eq(Cat(miso, miso_sr)),
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),
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If(~frame_stb,
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i_frame.eq(i_frame + 1),
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),
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If(frame_stb & clk_stb,
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i_frame.eq(0),
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self.crc.last.eq(0),
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# transpose, load
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Cat(sr).eq(Cat(words[mm::n_lanes] for mm in range(n_lanes))),
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Array([self.dat_r[i*n_frame//2:(i + 1)*n_frame//2]
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for i in range(1 << len(addr))])[addr].eq(miso_sr),
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addr.eq(addr + 1),
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),
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If(i_frame == n_div*n_frame//2 - 2,
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# inject crc
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ddr_data.eq(self.crc.next),
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),
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]
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clk_ddr = Signal()
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miso0 = Signal()
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self.specials += [
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DDROutput(clk[-1], clk[-2], clk_ddr, ClockSignal("rio_phy")),
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DifferentialOutput(clk_ddr, pins.clk, pins_n.clk),
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DifferentialInput(pins.miso, pins_n.miso, miso0),
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MultiReg(miso0, miso, "rio_phy"),
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]
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for sri, ddr, mp, mn in zip(
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sr, Signal(n_lanes), pins.mosi, pins_n.mosi):
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self.specials += [
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DDROutput(sri[-1], sri[-2], ddr, ClockSignal("rio_phy")),
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DifferentialOutput(ddr, mp, mn),
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]
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class Fastino(Module):
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def __init__(self, pins, pins_n):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=32, address_width=8,
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enable_replace=False),
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rtlink.IInterface(data_width=32))
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self.submodules.serializer = SerDes(pins, pins_n)
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# Support staging DAC data (in `dacs`) by writing to the
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# 32 DAC RTIO addresses, if a channel is not "held" by its
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# bit in `hold` the next frame will contain the update.
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# For the DACs held, the update is triggered by setting the
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# corresponding bit in `update`. Update is self-clearing.
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# This enables atomic DAC updates synchronized to a frame edge.
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#
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# This RTIO layout enables narrow RTIO words (32 bit
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# compared to 512), efficient few-channel updates,
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# least amount of DAC state tracking in kernels,
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# at the cost of more DMA and RTIO data ((n*(32+32+64) vs
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# 32+32*16+64))
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hold = Signal.like(self.serializer.enable)
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# TODO: stb, timestamp
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read_regs = Array([
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self.serializer.dat_r[i*7:(i + 1)*7]
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for i in range(1 << 4)
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])
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cases = {
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# update
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0x20: self.serializer.enable.eq(self.serializer.enable | self.rtlink.o.data),
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# hold
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0x21: hold.eq(self.rtlink.o.data),
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# cfg
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0x22: self.serializer.cfg[:4].eq(self.rtlink.o.data),
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# leds
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0x23: self.serializer.cfg[4:12].eq(self.rtlink.o.data),
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# reserved
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0x24: self.serializer.cfg[12:].eq(self.rtlink.o.data),
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}
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for i in range(len(self.serializer.dacs)):
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cases[i] = [
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self.serializer.dacs[i].eq(self.rtlink.o.data),
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If(~hold[i],
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self.serializer.enable[i].eq(1),
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)
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]
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self.sync.rio_phy += [
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If(self.serializer.stb,
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self.serializer.enable.eq(0),
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),
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If(self.rtlink.o.stb & ~self.rtlink.o.address[-1],
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Case(self.rtlink.o.address[:-1], cases),
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),
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]
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self.sync.rtio += [
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self.rtlink.i.stb.eq(self.rtlink.o.stb &
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self.rtlink.o.address[-1]),
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self.rtlink.i.data.eq(
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read_regs[self.rtlink.o.address[:-1]]),
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]
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@ -105,6 +105,12 @@ def peripheral_mirny(module, peripheral):
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eem.Mirny.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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def peripheral_fastino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Fastino.add_std(module, peripheral["ports"][0])
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peripheral_processors = {
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"dio": peripheral_dio,
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@ -115,6 +121,7 @@ peripheral_processors = {
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"zotino": peripheral_zotino,
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"grabber": peripheral_grabber,
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"mirny": peripheral_mirny,
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"fastino": peripheral_fastino,
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}
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@ -158,6 +158,12 @@ DAC/ADC drivers
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.. automodule:: artiq.coredevice.novogorny
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:members:
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:mod:`artiq.coredevice.fastino` module
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++++++++++++++++++++++++++++++++++++++++
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.. automodule:: artiq.coredevice.fastino
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:members:
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Miscellaneous
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-------------
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