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sayma_rtm: add basemod attenuators on RTIO
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@ -16,7 +16,7 @@ from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_a
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from misoc.integration.builder import Builder, builder_args, builder_argdict
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_serdes_7series
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerGTP
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@ -196,12 +196,23 @@ class Satellite(_SatelliteBase):
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platform = self.platform
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rtio_channels = []
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for i in range(4):
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phy = ttl_serdes_7series.Output_8X(platform.request("basemod0_rfsw", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(4):
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phy = ttl_serdes_7series.Output_8X(platform.request("basemod1_rfsw", i))
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for bm in range(2):
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print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}"
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.format(bm, len(rtio_channels)))
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for i in range(4):
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phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}"
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.format(bm, len(rtio_channels)))
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basemod_att = platform.request("basemod{}_att".format(bm))
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for name in "rst_n clk mosi le".split():
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signal = getattr(basemod_att, name)
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for i in range(len(signal)):
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phy = ttl_simple.Output(signal[i])
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.InOut(basemod_att.miso)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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