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Commit Graph

751 Commits

Author SHA1 Message Date
7c82fcf41a targets: avoid passing cpu_type around unnecessarily 2018-01-11 11:21:55 +08:00
6d58c4390b Merge branch 'sed-merge' 2018-01-10 13:14:39 +08:00
04b2fd3e13 sayma: fix AD9154NoSAWG ramp clock domain 2018-01-10 12:11:33 +08:00
dc593ec0f0 Merge branch 'rtio-sed' into sed-merge 2018-01-10 12:04:54 +08:00
Florent Kermarrec
2009734b3c serwb/phy: get 625Mbps linerate working, increase timeout 2018-01-09 18:54:52 +01:00
Florent Kermarrec
9c6a7f7509 serwb/kusphy: use same serwb_serdes_5x reset than s7phy 2018-01-09 18:54:05 +01:00
8813aee6b1 targets: add kasli [wip, untested] 2018-01-04 16:12:12 +01:00
Florent Kermarrec
1e972034e8 gateware/targets: enable serwb scrambling on sayma amc & rtm 2018-01-03 17:34:46 +01:00
Florent Kermarrec
907af25a69 gateware/serwb: add scrambling, reduce cdc fifo depth 2018-01-03 17:34:03 +01:00
Florent Kermarrec
7f4756a869 gateware/serwb: cleanup packet 2018-01-03 17:30:12 +01:00
c2be820e9a kc705_dds: make ext_clkout 100 MHz 2018-01-02 19:58:47 +01:00
43686f324b kc705_dds: fix HPC voltages
* VADJ is 3.3 V due to the DDS card on LPC
* the LVDS standards need to be 2.5 V

* the direction control register on HPC (FMC-DIO to VHDCI)
  was LVCMOS33 but while all the LVDS pairs are at VCCIO=VADJ=3.3 V
  they were instantiated as LVDS_25 (ignoring the wrongly powered bank)
* we now use 2.5 V standards on HPC consistently despite VADJ=3.3 V
  and hope for the best.
2018-01-02 13:41:07 +01:00
94b84ebe7c kc705_dds: add urukul spi/ttl channels 2018-01-02 13:20:48 +01:00
53969d3686 kc705_dds: add urukul on vhdci extension definition 2018-01-02 13:20:47 +01:00
2f8e6c7462 spi: add diff_term, save power on outputs 2018-01-02 13:20:47 +01:00
6d20b71dde ttl_serdes_7series: refactor IOSERDES 2018-01-02 13:20:47 +01:00
745e695b09 sayma: output a ramp in the absence of SAWG channels 2017-12-31 12:18:53 +01:00
whitequark
a371b25525 bootloader: allow using without Ethernet. 2017-12-31 09:21:28 +00:00
6e0288e568 drtio: fix GTH CPLL reset 2017-12-30 12:14:36 +08:00
379d29561b sayma: plausibility assertion on sawg data stream 2017-12-29 19:15:40 +01:00
37f9c0b10c spi: register clk
following m-labs/misoc#65
1dc68b0d0b
2017-12-28 16:50:22 +01:00
whitequark
acd13837ff firmware: implement the new bootloader. 2017-12-28 13:18:51 +00:00
8153cfa88f drtio/gth: add probes on {tx,rx}_init.done 2017-12-28 16:49:08 +08:00
c086149782 drtio/gth: use async microscope probes 2017-12-28 16:37:40 +08:00
whitequark
d94db1de5d Revert accidentally committed parts of 1b9b5602. 2017-12-28 08:23:34 +00:00
whitequark
1b9b560242 firmware: use libbuild_misoc in libdrtioaux. NFC. 2017-12-28 08:20:23 +00:00
6801921fc0 drtio: instrument GTH transceiver 2017-12-28 15:03:14 +08:00
70b7f28ad3 drtio: drive SFP TX disable pins 2017-12-23 22:58:51 +08:00
f8c8f3fe26 drtio: fix GTH clock domains 2017-12-23 07:21:44 +08:00
1af21c0b29 drtio: integrate GTH transceiver for Sayma 2017-12-23 01:19:59 +08:00
c57b66497c drtio: refactor/simplify GTH, use migen 2017-12-23 01:19:44 +08:00
77897228ca drtio: add GTH transceiver code from Florent (197c79d47) 2017-12-22 18:01:28 +08:00
ebdbaaad32 drtio: remove KC705/GTX support 2017-12-22 17:51:42 +08:00
0681d472c7 conda: fix sayma_rtm_csr.csv location for Sayma AMC 2017-12-22 17:14:10 +08:00
44959144d8 conda: add Sayma AMC standalone board package 2017-12-22 16:44:04 +08:00
Florent Kermarrec
86825a852c gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200 2017-12-21 23:52:44 +01:00
a6ffe9f38d drtio: add Sayma top-level designs 2017-12-21 23:08:56 +08:00
4fbc8772a5 sayma: allocate all user LEDs to RTIO, make one TTL SMA input 2017-12-21 19:27:38 +08:00
a23251276d Revert "sayma: set up Si5324 for RGMII clock rerouting"
This reverts commit 2b01aa22b6.
2017-12-21 14:42:15 +08:00
2b01aa22b6 sayma: set up Si5324 for RGMII clock rerouting 2017-12-17 00:25:33 +08:00
b6199bb35b sayma: style 2017-12-15 19:45:51 +08:00
649b60ea29 targets/kc705_drtio: remove DAC FMC card support 2017-12-15 17:32:25 +08:00
341e809859 targets/sayma_rtm: enable Allaki RF switches, GPIO access to attenuator 2017-12-15 13:08:35 +08:00
569484f888 remove phaser, adapt SAWG example to Sayma 2017-12-14 18:49:27 +08:00
5e251cd85c sayma_amc: remove redundant bitstream options
* CONFIGRATE default is sufficient
* SPI width can be auto and QSPI works
2017-12-13 14:39:32 +01:00
a9d0f253a5 sayma_amc: set bitstream and config parameters
* slow down CCLK rate as there is additional loading
  on the signals
* single bit SPI for now until we know that quad SPI
  works
* set up

https://github.com/m-labs/artiq/issues/847
2017-12-13 21:21:52 +08:00
whitequark
1c25f7ef52 gateware: make software builds spew less junk on the console.
[ci skip]
2017-12-04 14:19:35 +00:00
bb3d6ef84a sayma: remove ad9154 from mem_map
Address is autogenerated by CSR system.
2017-11-29 18:17:25 +08:00
ecfe2e40ee sayma_amc_standalone: rtio channels for both sawg groups 2017-11-19 18:32:42 +01:00
d1a7c1c3a1 sayma_amc_standalone: connect sawg to jesd again 2017-11-19 14:36:20 +01:00