d0cf0f2b87
sawg/limiter: make signed signals explicitly
2017-06-22 13:44:36 +02:00
694f8d784c
dsp/tools: unittest sat_add
2017-06-22 11:29:56 +02:00
bd1438d28e
sawg: wrap limits init values
2017-06-22 10:26:29 +02:00
cccd01e81e
sawg: cleanup sat_add logic
2017-06-22 10:26:29 +02:00
5f6e665158
test/sawg: patch delay_mu
2017-06-22 10:26:29 +02:00
570f2cc1ff
dsp/tools/SatAdd: fix reuse of clipped signal
2017-06-22 10:26:29 +02:00
4b3aad2563
sawg: clean up Config
...
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
2017-06-22 10:26:29 +02:00
f4c6879c76
sawg: special case Config RTIO address
2017-06-22 10:26:29 +02:00
ff0da2c9fc
sawg: stage code for y-data exchange on channels
2017-06-22 10:26:29 +02:00
b6569df02f
dsp/tools: clean up SatAddMixin logic
2017-06-22 10:26:29 +02:00
74cf074538
drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times
2017-06-21 17:01:52 +08:00
0d8067256b
rtio: refactor RelaxedAsyncResetSynchronizer
2017-06-18 14:37:08 +02:00
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
219dfd8984
rtio: add one register level for rio and rio_phy resets
...
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
e19bfd4781
test_sawg_fe: add ref_multiplier to simulated core
2017-06-16 19:45:24 +02:00
2a76034fbc
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
3f37870e25
sawg: register pre-hbf adder
2017-06-13 18:15:44 +02:00
e229edd5d5
sawg: add register after hbf for timing
2017-06-12 23:08:27 +02:00
315338fca9
test/sawg: test HBF overshoot, fix sim patching
2017-06-12 20:35:47 +02:00
9a8a7b9102
sawg: handle clipping interpolator
...
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC
This leaves a factor of two headroom for the sum of the following
effects:
* HBF overshoot (~15 % of the step)
* A1/A2 DDS sum
While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?
closes #743
2017-06-12 20:33:54 +02:00
1fb3995ffc
Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)"
...
This reverts commit 6ac9d0c41e
2017-06-12 20:07:25 +02:00
332bcc7f3b
fir: check widths
2017-06-12 20:07:23 +02:00
39a1dcbb3d
test/fir: look at overshoot behavior
2017-06-12 20:06:07 +02:00
6ac9d0c41e
fir/ParallelHBFUpsampler: add headroom (gain=2)
...
This addresses part of #743
2017-06-12 18:59:45 +02:00
bfc224d4ba
phaser: adjust to new jesd
2017-05-22 19:59:53 +02:00
679060af1d
phaser: enable dma
2017-05-22 19:32:34 +02:00
4901cb9a8a
sawg: fix clr width
2017-05-22 17:46:55 +02:00
253ee950f6
sawg: fix config channel addr
2017-05-22 17:45:14 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
170d2886fd
Merge branch 'pdq'
...
* pdq:
pdq: documentation
pdq2 -> pdq
pdq2: use 16 bit data, buffered read_mem()
spi: style
pdq2: mem_read
pdq2: align subsequent writes to end
sma_spi: undo cri_con
pdq2: memory write, kernel_invariants
sma_spi: cri/cd changes
sma_spi: LVCMOS25
coredevice.spi: kernel invariants and style
sma_spi: free up user_sma pins
sma_spi: add demo target with SPI on four SMA
pdq2: memory write
pdq2: crc/frame register accessors
doc: pdq2 spi backend
pdq2: config writes
2017-05-12 11:46:45 +02:00
Florent Kermarrec
79c339d4ac
gateware/targets/phaser: jesd core now handles jsync completely
2017-04-26 22:25:08 +02:00
Florent Kermarrec
0546affd4c
gateware/target/phaser: jesd start signal renamed to jsync
2017-04-26 12:27:40 +02:00
ed8edf318d
sma_spi: undo cri_con
2017-04-08 17:19:35 +02:00
16b7f8f50c
sma_spi: cri/cd changes
2017-04-08 17:16:19 +02:00
1e6e81a19e
sma_spi: LVCMOS25
2017-04-08 17:16:19 +02:00
555b3c38c1
sma_spi: free up user_sma pins
2017-04-08 17:16:19 +02:00
2c7c6143ab
sma_spi: add demo target with SPI on four SMA
2017-04-08 17:16:19 +02:00
c2667debf8
drtio: test replace in RTL simulation
2017-04-06 16:33:59 +08:00
729e7b52f0
drtio: collision/replace fixes
2017-04-06 16:33:49 +08:00
83d87b5805
drtio: remove outdated comment
2017-04-06 12:45:10 +08:00
c0100ebc56
rtio: fix indentation
2017-04-06 12:08:13 +08:00
207453efcd
rtio: add a missing case for collision reporting
2017-04-06 11:28:16 +08:00
674bf82f3a
gateware: add cri_con CSRs to all DMA-capable targets
2017-04-06 01:14:09 +08:00
5e3aef45dc
drtio: support collision/replace + detect sequence errors at satellite
2017-04-06 01:06:56 +08:00
whitequark
17b5388259
gateware: remove one stray CRI arbiter remnant.
2017-04-05 16:38:56 +00:00
whitequark
464202d0aa
gateware: connect CRI switch to kernel CPU.
2017-04-05 16:10:53 +00:00
whitequark
47632f81b1
gateware: CRIArbiter -> CRISwitch.
2017-04-05 16:10:39 +00:00
whitequark
391660e545
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
12249dac57
rtio: do not clear asynchronous error flags on RTIO reset
2017-04-03 00:20:30 +08:00
db3118b916
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
8c414cebc7
drtio: report busy errors
2017-04-03 00:11:08 +08:00
008678b741
drtio: add infrastructure for reporting busy/collision errors
2017-04-02 23:45:55 +08:00
0a687b7902
drtio: report satellite errors through firmware
2017-04-01 12:18:00 +08:00
28211e0b32
gateware: reset RTIO DMA core when kernel CPU is reset
2017-03-31 15:35:28 +08:00
200c499114
test: change base address in DMA simulation testbench
2017-03-31 13:17:00 +08:00
ea3af1e20e
drtio: remove obsolete CSR accesses from test
2017-03-27 16:44:22 +08:00
b74d6fb9ba
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
whitequark
4de336fbe9
gateware: reverse bytes of SDRAM word, not bits.
2017-03-17 11:16:46 +00:00
whitequark
6b63322106
gateware: reverse SDRAM words in RTIO DMA engine.
2017-03-17 07:29:28 +00:00
whitequark
4b14887ddb
gateware: work around ISE/Vivado bugs with very wide shifts.
2017-03-17 07:29:28 +00:00
whitequark
4beda73217
firmware: don't build libdyld through misoc.
2017-03-14 08:33:31 +00:00
a7de58b604
rtio: Inout → InOut
2017-03-14 14:18:55 +08:00
13ae1d1a38
drtio: input unittest
2017-03-14 14:14:55 +08:00
56fd9b3b4b
drtio: input fixes
2017-03-14 14:14:43 +08:00
95ede18809
drtio: support PHY latency compensation
2017-03-14 00:01:38 +08:00
497c795d8c
drtio: input support (untested)
2017-03-13 23:54:44 +08:00
d1b9f9d737
drtio: rt_packets → rt_packet
2017-03-13 00:10:07 +08:00
6b7c781ff2
drtio: introduce 'standard request' interface in RT packet layer
2017-03-13 00:08:03 +08:00
2b8729f326
drtio: clear any read request on satellite reset
2017-03-13 00:00:38 +08:00
1e47e638bb
drtio: implement inputs in RTPacketSatellite, reorganize code
2017-03-07 00:46:59 +08:00
1e6a33b586
rtio: handle input timeout in gateware
...
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
2017-03-03 17:37:47 +08:00
d2f2415b50
analyzer: use CRI and connect at RTIO core
...
This causes DMA events to be included in analyzer traces.
2017-03-02 18:47:56 +08:00
7d6ebabc1b
reorganize core device communication code
2017-02-27 18:37:30 +08:00
f017d1771f
gateware: remove unused configs in targets (not needed with new moninj)
2017-02-25 12:14:56 +08:00
360be0098f
drtio: map local RTIO core on lower channels
2017-02-24 18:15:27 +08:00
b455ea447d
gateware: add moninj to drtio targets
2017-02-21 21:54:47 +08:00
c66efc0279
moninj: do not require a rsys clock domain
2017-02-20 15:52:48 +08:00
c022b53578
kernel_cpu: enable perf counters
2017-02-18 14:09:12 +01:00
935799dfb7
drtio: fix satellite transceiver clocking
2017-02-04 19:18:35 +08:00
whitequark
b9cbedceb1
firmware: migrate last vestiges of the old runtime build system.
2017-02-03 12:59:35 +00:00
a8ecbd6041
firmware: do not attempt to build Si5324 code when gateware does not support it
2017-02-03 12:27:13 +08:00
d181989de9
drtio: reset Si5324 at each boot
2017-02-03 12:00:58 +08:00
b3697f951a
drtio: forward clocks to SMA connectors for debugging
2017-02-03 12:00:36 +08:00
aafefee7f5
targets: make number of ethmac slots consistent
2017-02-02 23:02:51 +08:00
whitequark
44a9a79f96
firmware: port allocator to Rust.
2017-02-02 10:55:35 +00:00
f512ea42dc
drtio: initialize si5324 in firmware
2017-02-02 18:11:24 +08:00
whitequark
b95db4fa4e
Use four ethmac buffers instead of two.
...
This should address an issue where the host sends a packet burst,
the second packet in a burst gets dropped, the rest also gets
dropped since smoltcp doesn't do reassembly, and the entire dance
is repeated on every retransmit.
2017-01-30 07:42:27 +00:00
9800acea92
drtio: program Si5324 for 150MHz in 3G config
2017-01-30 14:50:12 +08:00
7daab07a29
drtio: fix syntax/import
2017-01-30 13:01:45 +08:00
d8e9949266
drtio: initialize AD9516 clock chip
2017-01-30 11:06:45 +08:00
f6024b6c9a
drtio: fix ad9154 extension registration
2017-01-30 10:59:22 +08:00
43aad0914e
python3.5 -> python3
...
Many things also work with Python 3.6.
2017-01-30 09:24:43 +08:00
657afd770e
artiq/test/gateware -> artiq/gateware/test
...
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
2017-01-30 09:00:55 +08:00
94b0783897
drtio: remove support for transceiver SMAs
...
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
2017-01-27 23:33:50 +08:00
whitequark
de17908b38
Revert "Globally update UART baudrate to 921600."
...
This reverts commit b29e2d5bfe
2017-01-25 00:31:28 +00:00
whitequark
b29e2d5bfe
Globally update UART baudrate to 921600.
2017-01-24 22:25:58 +00:00
whitequark
527b1e986c
firmware: integrate smoltcp instead of lwip.
2017-01-23 13:59:34 +00:00
28a41a2f60
gateware: fix aeb1ba847
2017-01-18 17:11:02 -06:00
2a7a8f91ca
gateware: fix import
2017-01-18 16:51:30 -06:00
ce31ffddb0
firmware: add satellite manager
...
The code duplication with the runtime should be cleaned up later.
2017-01-18 16:50:32 -06:00
b40953800a
gateware: soc -> amp.soc
2017-01-18 15:28:14 -06:00
aeb1ba8471
gateware: use default MiSoC timer
2017-01-18 15:22:33 -06:00
b8d89d56b1
drtio: add GenericRXSynchronizer
2017-01-15 13:44:43 -06:00
0edffb54c2
drtio: fix packet truncation detection in RTPacketSatellite
2017-01-13 09:29:22 -06:00
6805feb494
drtio: report truncated packets
2017-01-12 23:44:45 -06:00
7c699e2f80
drtio: add FIFO space request count debug API
2017-01-11 13:48:14 -06:00
c25186fae1
drtio: print packet error descriptions in log
2017-01-10 18:03:01 -06:00
98598df78e
rtio: keep retrying on get FIFO space timeout
2017-01-10 16:12:32 -06:00
e624f45369
drtio: remove FIFO empty local detection optimization
...
It optimizes a marginal case, it is difficult to get right
(need to know the size of the FIFO for each channel), and
it adds complexity and potential bug sources.
2017-01-10 14:31:46 -06:00
f75fffcf96
drtio: fix satellite RX data corruption
2017-01-10 14:29:30 -06:00
fe53bab953
targets: kc705 -> kc705_dds
2017-01-05 18:40:56 +01:00
082fdaf450
move i2c to libboard, do bit-banging on comms CPU
2017-01-04 21:04:38 +01:00
86f6b391b7
ad9xxx -> ad9_dds
2017-01-04 11:34:52 +01:00
c08fc8aae9
firmware: support moninj without DDS. Closes #650
2017-01-04 11:26:02 +01:00
455250b3f9
remove DDS_AD9914 and DDS_ONEHOT_SEL
2017-01-03 22:04:25 +01:00
fbf5a4d4a2
Merge branch 'phaser2-rust-init'
2017-01-03 21:31:21 +01:00
9a80b8d533
spi: fix xfers with full data_width ( closes #615 )
...
misoc 15000af43611bbe8be13cb2b016e408f043202cd
2017-01-03 19:51:14 +01:00
7ff77bceac
move AD9616 and AD9154 initialization to firmware
2017-01-03 16:11:38 +01:00
417708af90
phaser: add note about DDS defines ( #650 )
2017-01-02 22:15:21 +01:00
f5f662200b
fir: streamline, optimize DSP extraction, left-align inputs
2016-12-20 21:39:51 +01:00
cfb66117af
fir: size hint for pre-adder
2016-12-20 17:58:06 +01:00
f310274e39
fir: cleanup halfgen4
2016-12-20 17:58:06 +01:00
6b998581cc
rtio: use same reset for counter_rtio whatever the interface delay is
2016-12-15 09:28:13 +08:00
115ea67860
fir: automatically use transposed topology
2016-12-14 19:16:07 +01:00
a451b675c9
Revert "fir: different adder layout"
...
This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866.
2016-12-14 19:16:07 +01:00
93076b8efa
fir: different adder layout
2016-12-14 19:16:07 +01:00
61abd994e9
Revert "fir: force dsp48"
...
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
2016-12-14 19:16:07 +01:00
641d109786
fir: force dsp48
2016-12-14 19:16:07 +01:00
8381db279f
sawg: wire up all HBF outputs, latency compensation in phys, simplify
2016-12-14 19:16:07 +01:00
6cdb96c5e0
rtio: add support for latency compensation in phy
...
* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
2016-12-14 19:16:07 +01:00
4c27029be0
sawg: fix limit regs
2016-12-14 19:16:07 +01:00
e9592105ce
drtio: fix aux controller clock domain mistakes
2016-12-14 10:16:45 +08:00
527757b471
kc705_drtio: use ad9154_fmc_ebz
2016-12-13 14:30:26 +08:00
3b5abae935
drtio: fix clock domain conflict
2016-12-13 14:19:49 +08:00
03d13d3811
phaser: dma/drtio changes
2016-12-12 17:46:36 +01:00
c63fa46430
Merge branch 'phaser2'
...
* phaser2: (157 commits)
sawg/hbf: tweak pipeline for timing
fir: register multiplier output
conda/phaser: build-depend on numpy
sawg: reduce coefficient width
sawg: fix latency
test/fir: needs mpl. don't run by default
test/sawg: patch spline
sawg: use ParallelHBFCascade to AA [WIP]
fir: add ParallelHBFCascade
fir: add ParallelFIR and test
gateware/dsp: add FIR and test
README_PHASER: update
sawg: documentation
sawg: extract spline
sawg: document
sawg: demo_2tone
sawg: round to int64
gateware/phaser -> gateware/ad9154_fmc_ebz
phaser: fix typo
sawg: merge set/set64
...
2016-12-12 17:31:39 +01:00
4b61020b27
drtio: reset more local state
2016-12-12 18:48:10 +08:00
d99e64effd
drtio: clear any stale FIFO space reply
2016-12-12 18:02:56 +08:00
4c59c0fecf
Revert "drtio: order resets wrt writes"
...
This reverts commit 9a048c2b3a
2016-12-12 17:49:07 +08:00
8f747fa209
drtio: clear underflow and sequence error on reset
2016-12-12 17:39:14 +08:00
7196bc21c1
rtio: simplify error reset logic
...
Channel is always selected when reset is issued.
2016-12-12 17:35:10 +08:00
9a048c2b3a
drtio: order resets wrt writes
2016-12-12 17:18:07 +08:00
0a9f69a3ed
kc705_drtio_master: add missing rtio_core CSRs
2016-12-09 19:23:36 +08:00
bc36bda94a
perform RTIO init on comms CPU side
2016-12-09 14:16:55 +08:00
f6071a5812
sawg/hbf: tweak pipeline for timing
2016-12-08 17:00:53 +01:00
b7a308d33d
fir: register multiplier output
2016-12-08 17:00:39 +01:00
18e3f58c22
sawg: reduce coefficient width
2016-12-08 16:14:32 +01:00
598da09a93
sawg: fix latency
2016-12-08 15:53:35 +01:00
3eef6229cc
sawg: use ParallelHBFCascade to AA [WIP]
2016-12-08 15:32:57 +01:00
a629eb1665
fir: add ParallelHBFCascade
2016-12-08 15:30:26 +01:00
d303225249
fir: add ParallelFIR and test
2016-12-08 15:21:04 +01:00
7e0f3edca5
gateware/dsp: add FIR and test
2016-12-07 19:14:23 +01:00
4c3717932e
drtio: link layer debugging CSRs
2016-12-07 23:03:14 +08:00
b311830fc4
kc705: fix drtio_aux address conflict
2016-12-06 18:28:48 +08:00
4669d3f02f
kc705_drtio_satellite: add MiSoC system, hook up auxiliary controller
2016-12-06 14:56:42 +08:00
f4b7d39a69
kc705_drtio_master: hook up auxiliary controller
2016-12-06 14:56:15 +08:00
f3c50a37ca
rtio: always read full DMA sequence
2016-12-06 01:05:47 +08:00
c413d95b49
rtio: fix DMA get_csrs
2016-12-05 18:12:09 +08:00
b677c69faf
rtio: fix handling of o_status in DMA
2016-12-05 18:01:48 +08:00
75ea13748a
rtio: fix DMA data MSB and stop signaling, self-checking unittest
2016-12-05 18:01:48 +08:00
a5834765d0
rtio: more DMA fixes, better stopping mechanism
2016-12-05 18:01:48 +08:00
30bce5ad35
rtio: DMA fixes
2016-12-05 18:01:48 +08:00
88ad054ab6
Merge branch 'drtio'
2016-12-03 23:25:17 +08:00
5d145ff912
drtio: add false paths between sys and transceiver clocks
2016-12-03 23:03:01 +08:00
4b97b9f8ce
drtio: add clock constraints
2016-12-03 22:17:29 +08:00
e747696aaa
Merge remote-tracking branch 'm-labs/phaser2' into phaser2
...
* m-labs/phaser2:
phaser: fix typo
2016-12-02 14:11:56 +01:00
cbf1004df3
gateware/phaser -> gateware/ad9154_fmc_ebz
2016-12-02 14:11:41 +01:00
6353f6d590
drtio: support different configurations and speeds
2016-12-02 17:22:22 +08:00
3cee269afe
phaser: fix typo
2016-12-02 11:06:45 +08:00
3931d8097b
rtio: fix DMA TimeOffset stream.connect
2016-12-01 16:43:46 +08:00
d4cb1eb998
kc705: integrate DMA
2016-12-01 16:31:00 +08:00
7c59688a12
rtio: simple DMA fixes
2016-12-01 16:30:48 +08:00
46dbc44c8f
rtio: export DMA and CRIInterconnectShared
2016-12-01 16:30:29 +08:00
6c97a97d8c
rtio: support single-master CRI arbiter
2016-12-01 16:30:11 +08:00
a318243083
rtio: CRI arbiter (untested)
2016-12-01 15:41:43 +08:00
cd3f68ba76
rtio: DMA core (untested)
2016-11-30 18:43:19 +08:00
d8b5eac856
sawg: style
2016-11-29 20:51:40 +01:00
27160f5912
phaser: make sysref input only for timing
2016-11-29 15:28:10 +01:00
cf342eca6e
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-29 10:44:27 +08:00
f4c6d6eb69
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-28 15:18:54 +08:00
85f2467e2c
rtio: fix RTIO/DRTIO timestamp resolution discrepancy
2016-11-28 15:01:46 +08:00
9fdd29ddae
drtio: connect KernelInitiator correctly
2016-11-28 14:36:18 +08:00
5460202220
drtio: typo
2016-11-28 14:35:21 +08:00
4e1b497742
drtio: typo
2016-11-28 14:34:58 +08:00
c419c422fa
drtio: support for local RTIO core
2016-11-28 14:33:26 +08:00
046b8bfd33
drtio: fix transmit datapath with transceiver width > max packet width
2016-11-27 13:19:12 +08:00
0903964488
drtio: large data fixes
2016-11-27 02:12:50 +08:00
8090abef5d
drtio: large data support
2016-11-25 17:04:09 +08:00
55e37b41ec
phaser: use ttl_simple.Input for sync
2016-11-24 15:55:26 +01:00
8060652913
phaser: use Inout_8X
2016-11-24 15:21:03 +01:00
617650f3b2
phaser: extract target
2016-11-24 15:20:51 +01:00
1c84d1ee59
Merge branch 'master' into phaser2
...
* master:
rtio: support differential ttl
RELEASE_NOTES: int(a, width=b) removal, use int32/64
pc_rpc: use ProactorEventLoop on Windows (#627 )
2016-11-24 15:05:49 +01:00
95c885b580
rtio: support differential ttl
2016-11-24 15:04:12 +01:00
7cd27abaa6
drtio: do not reset remote TSC on reset command
2016-11-24 00:09:53 +08:00
2d62a89143
rtio: use large data register
2016-11-23 23:23:27 +08:00
07f2d84275
drtio: remote resets
2016-11-23 23:19:31 +08:00
9941f3557d
rtio: use only CRI commands for rio/rio_phy resets
2016-11-23 23:19:14 +08:00
347609d765
rtio: auto clear output event data and address
...
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-23 15:03:36 +01:00
32fdacd95a
Merge remote-tracking branch 'm-labs/master' into phaser2
...
* m-labs/master:
runtime: don't attempt to perform writeback if disabled in kernel.
runtime: print trace level log messages to UART during startup.
runtime: support for targets without RTIO log channel
runtime: support for targets without I2C
kc705: remove stale DDS definition
runtime: show a prompt to erase startup/idle kernels.
2016-11-23 14:56:29 +01:00
d400c81cb2
rtio: remove debug print
2016-11-23 13:37:14 +08:00
4e931c7dd2
rtio: fix timestamp shift
2016-11-23 13:36:30 +08:00
e532261a9b
drtio: fix FullMemoryWE usage
2016-11-23 12:25:43 +08:00
0443f83d5e
runtime: support for targets without RTIO log channel
2016-11-23 10:50:55 +08:00
0c49679984
runtime: support for targets without RTIO log channel
2016-11-23 10:48:26 +08:00
ffefdb9269
rtio: fix counter readback
2016-11-23 00:54:47 +08:00
aa00627c0e
rtio: fix CRI CSRs
2016-11-22 22:57:04 +08:00
fbd83cf9ee
kc705: remove stale DDS definition
2016-11-22 22:48:22 +08:00
9acc7d135e
gateware: common RTIO interface
2016-11-22 22:46:50 +08:00
0aaf120ca7
kc705: remove stale DDS definition
2016-11-22 22:46:19 +08:00
3459793586
Merge branch 'master' into drtio
2016-11-22 15:15:22 +08:00
4160490e0a
Merge branch 'phaser' into phaser2
...
* phaser: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:46 +01:00
f7e8961ab0
Merge branch 'master' into phaser
...
* master: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:39 +01:00
93c310dfa5
pipistrello: add some inputs
2016-11-21 23:43:41 +08:00
whitequark
6aa5d9f6c6
Remove last vestiges of nist_qc1.
2016-11-21 15:36:22 +00:00
whitequark
5e8888d5f3
Fully drop AD9858 and kc705-nist_qc1 support ( closes #576 ).
2016-11-21 15:14:17 +00:00
whitequark
f4b7666768
coredevice.dds: reimplement fully in ARTIQ Python.
...
This commit also drops AD9858 support from software.
2016-11-21 15:13:26 +00:00
174c4be218
phaser: false paths sys<->{jesd,phy.tx}
2016-11-21 09:57:33 +01:00
74e5013fe5
sawg: fix b delay width
2016-11-20 16:39:22 +01:00
ad1049d59a
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
...
This reverts commit 4a62e09bd4
2016-11-20 21:35:07 +08:00
whitequark
30598720f4
Fix whitespace.
2016-11-20 09:50:00 +00:00
David Leibrandt
4a62e09bd4
gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623
2016-11-20 15:22:32 +08:00
12e39a64cf
sawg: reduce f0 oscillator width to 32
2016-11-19 17:07:07 +01:00
04813ea29b
sawg: wir up limiting, saturating addition
2016-11-19 16:12:27 +01:00
e53d0bcd5b
dsp: add limits support to SatAddMixin
2016-11-19 16:12:27 +01:00
97a54046e8
rtio: auto clear output event data and address
...
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-19 16:12:27 +01:00
b714137f76
phaser: 150 MHz rtio/jesd clock
2016-11-19 13:16:30 +01:00
02adae7397
drtio: fix link shutdown
2016-11-19 11:01:33 +08:00
381e58434f
drtio: handle link restarts at transceiver level
2016-11-19 10:46:56 +08:00
0ee47e77ae
phaser: fix widths
2016-11-18 17:24:11 +01:00
bcde26f990
Revert "phaser: cap phy data width to 64 temporarily"
...
This reverts commit 342b9e977e
2016-11-18 17:08:44 +01:00
ba94ed8f4b
drtio: check for absence of disparity errors before claiming RX ready
2016-11-19 00:05:59 +08:00
342b9e977e
phaser: cap phy data width to 64 temporarily
2016-11-18 15:46:59 +01:00
14ddcd2e30
Revert "dsp/Delay: reset_less"
...
for now
This reverts commit 98193d6fa1
2016-11-18 15:25:42 +01:00
d678bb3fb6
phaser: update sawg tests
2016-11-18 15:23:56 +01:00
4d07974a34
drtio: reset link from CPU
2016-11-18 17:45:33 +08:00
f040e27041
drtio: add timeout on FIFO get space request
2016-11-18 17:44:48 +08:00
bb047aabe9
drtio: simpler link layer
2016-11-17 22:32:39 +08:00
51f23feeac
dsp: implement sawg features
2016-11-17 03:20:37 +01:00
98193d6fa1
dsp/Delay: reset_less
2016-11-17 02:36:29 +01:00
424a1f8f4e
dsp: move test tools
2016-11-16 13:39:19 +01:00
140bb0ecee
drtio: aux controller fixes
2016-11-16 19:44:03 +08:00
6c9965b444
drtio: aux controller fixes
2016-11-15 12:02:41 +08:00
e1394db861
drtio: aux controller minor fixes
2016-11-14 17:26:30 +08:00
84bd962ed5
drtio: integrate aux controller
2016-11-14 17:20:47 +08:00
a4d92716da
drtio: fix aux receiver, add aux transmitter
2016-11-14 17:18:54 +08:00
b9ce2bb1f0
Merge branch 'phaser' into phaser2
...
* phaser: (127 commits)
phaser: use misoc cordic
phaser: fix DDS dummy cfg
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
...
2016-11-13 17:30:37 +01:00
70a70320bd
phaser: use misoc cordic
2016-11-13 17:29:38 +01:00
2e482505c6
phaser: fix DDS dummy cfg
2016-11-13 17:08:59 +01:00
f2f131e0fb
drtio: add aux receiver (untested)
2016-11-14 00:04:53 +08:00
aedb6747f2
Merge branch 'master' into phaser
...
* master: (47 commits)
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
Revert "Revert "Revert "Revert "Update for LLVM 3.9.""""
Revert "Revert "Revert "Update for LLVM 3.9."""
...
2016-11-13 16:54:28 +01:00
