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f988ec318e
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pipistrello: fix csrs, make AMP default
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2015-04-14 21:10:07 -06:00 |
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9e726d7dd1
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ppro: ignore all async paths
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2015-04-14 18:18:48 -06:00 |
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70916aa0c5
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pipistrello: tig _all_ async paths, add timing interference report
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2015-04-14 18:18:48 -06:00 |
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066adbdeac
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pipistrello: timing report
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2015-04-14 18:18:16 -06:00 |
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6217cf5392
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pipistrello: basesoc, cleanup
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2015-04-14 18:18:16 -06:00 |
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4c10182c9f
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rtio: refactor, use rtlink
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2015-04-14 19:44:45 +08:00 |
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c0f1708c20
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targets/pipstrello: fix mem_map
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2015-04-14 19:34:14 +08:00 |
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a50f2c20ff
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targets/ppro: fix mem_map update
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2015-04-11 21:59:29 +08:00 |
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601f593ac4
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targets/kc705: do not depend on particular Migen generated signal names
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2015-04-11 21:46:57 +08:00 |
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Florent Kermarrec
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bdd02a064e
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targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)
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2015-04-11 21:32:46 +08:00 |
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Florent Kermarrec
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24b2bd7b6f
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soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds
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2015-04-11 21:32:11 +08:00 |
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fb75bd246e
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targets/kc705: make AMP the default
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2015-04-11 17:16:25 +08:00 |
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b492aad1c4
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targets/kc705: enable Ethernet core
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2015-04-10 13:15:32 +08:00 |
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44304a33b2
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soc,runtime: define RTIO FUD channel number in targets
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2015-04-09 00:35:11 +08:00 |
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7e591bb1c7
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targets: use _Peripherals/UP/AMP class names, share QC1 IO defs
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2015-04-07 00:07:53 +08:00 |
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ef375b5c9c
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pipistrello: add double-cpu
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2015-04-04 20:52:08 -06:00 |
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afc3982555
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pipistrello: refactor single-cpu
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2015-04-04 20:51:47 -06:00 |
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0ae4492077
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pipistrello: use mem_decoder
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2015-04-04 20:51:47 -06:00 |
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e50661dac4
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pipistrello: fix dcm parameters, move leds, fix names
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2015-04-04 20:51:47 -06:00 |
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277e038569
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targets/kc705: add LED on RTIO
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2015-04-04 22:07:23 +08:00 |
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5f7161a7de
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kc705: 16 TTLs
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2015-04-03 15:57:25 +08:00 |
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Florent Kermarrec
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2995f0a705
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remove use of _r prefix on CSRs
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2015-04-02 18:30:44 +08:00 |
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88a1707ef9
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soc: use new location of gpio module
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2015-04-02 17:19:00 +08:00 |
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5fd7f68f48
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targets/kc705: dual-CPU design
|
2015-04-02 16:53:57 +08:00 |
|
Yann Sionneau
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e9092edb98
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Remove one RTIO out channel to free up some space for travis builds to succeed
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2015-03-30 19:51:52 +08:00 |
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Florent Kermarrec
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494c670cd2
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targets/artiq_ppro: use new sdram_controller_settings parameter
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2015-03-21 23:19:16 +01:00 |
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fdca0a71ff
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add ARTIQMidiSoC based on pipistrello
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2015-03-19 11:37:15 -06:00 |
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3122623c6f
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rtio: make 63-bit timestamp counter the default [soc]
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2015-03-12 13:13:35 +01:00 |
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28bce9ee40
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artiqlib -> artiq.gateware
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2015-03-08 11:00:24 +01:00 |
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4e5320be28
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Merge branch 'master' of https://github.com/m-labs/artiq
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2015-02-28 07:34:38 -07:00 |
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Florent Kermarrec
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9cf8db2f14
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adapt code to MiSoC's changes
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2015-02-28 07:34:11 -07:00 |
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7028d85255
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targets/ppro: disable L2
|
2015-02-27 18:02:21 -07:00 |
|
Joe Britton
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0127de9bb5
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soc: add_cpu_csr_region -> add_csr_region
|
2015-02-27 15:02:28 -07:00 |
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|
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da917f768e
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initial kc705 support
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2015-02-26 21:50:52 -07:00 |
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c591f1a74d
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targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG
|
2014-12-01 18:53:29 +08:00 |
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99d530e498
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targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
|
2014-12-01 17:31:35 +08:00 |
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7166ca82d1
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targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
|
2014-11-30 22:31:55 +08:00 |
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1f6441948d
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more TTL channels and larger input FIFOs on Papilio Pro
|
2014-11-30 15:50:57 +08:00 |
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39c4b5416f
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targets/ARTIQMiniSoC: 125MHz RTIO clocking
|
2014-11-30 01:00:27 +08:00 |
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901073acf3
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asynchronous RTIO
|
2014-11-30 00:13:54 +08:00 |
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44ec3eae3d
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soc/target: use minicon by default
|
2014-11-28 10:21:43 +08:00 |
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65567e1201
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soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY
|
2014-11-21 15:51:51 -08:00 |
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346cca9e90
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soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC
|
2014-10-21 18:40:08 +08:00 |
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af0cd902d3
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get frequency from RTIO, support fractional frequencies
|
2014-09-26 17:24:06 +08:00 |
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f0f65ba3a7
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soc/target: add optional test signal generator
|
2014-09-17 19:53:55 +08:00 |
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2c0b6ff4cc
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soc/target: connect FUD to RTIO
|
2014-09-11 23:11:22 +08:00 |
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|
|
8d7591dfcf
|
more PEP8
|
2014-09-05 17:06:41 +08:00 |
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4915b4b5aa
|
PEP8
|
2014-09-05 12:03:22 +08:00 |
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1ed808e848
|
soc/target: share base PPro design with MiSoC
|
2014-08-03 12:26:15 +08:00 |
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f03ae5e5b0
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soc/rtio: separate PHY, add OE and fine timestamp in FIFO
|
2014-07-24 23:50:20 -06:00 |
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005d66c7cd
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soc/dds: fix timing
|
2014-07-22 17:44:41 -06:00 |
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2358b218bf
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soc: add DDS interface core
|
2014-07-22 11:37:53 -06:00 |
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5573cf3688
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soc: add tester IO
|
2014-07-22 10:45:59 -06:00 |
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ede3667fd3
|
soc/target: use only 8 TTL channels for now
|
2014-07-20 18:38:41 -06:00 |
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|
3b4bb41a19
|
add basic output-only untested RTIO core
|
2014-07-16 19:13:11 -06:00 |
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|
d804f1199e
|
soc: add LED
|
2014-07-05 22:44:20 +02:00 |
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|
|
6072f0c42f
|
Basic SoC and runtime design
|
2014-07-04 17:49:08 +02:00 |
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