mirror of https://github.com/m-labs/artiq.git
asynchronous RTIO
This commit is contained in:
parent
9c41f98d70
commit
901073acf3
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@ -107,7 +107,8 @@ class RTIOOut(_RTIOBase):
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the output of the DDS).
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"""
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syscall("rtio_sync", self.channel)
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while syscall("rtio_get_counter") < self.previous_timestamp:
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pass
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@kernel
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def on(self):
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@ -192,7 +193,7 @@ class RTIOIn(_RTIOBase):
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"""
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count = 0
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while syscall("rtio_get", self.channel) >= 0:
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while syscall("rtio_get", self.channel, self.previous_timestamp) >= 0:
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count += 1
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return count
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@ -204,4 +205,5 @@ class RTIOIn(_RTIOBase):
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If the gate is permanently closed, returns a negative value.
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"""
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return cycles_to_time(syscall("rtio_get", self.channel))
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return cycles_to_time(syscall("rtio_get", self.channel,
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self.previous_timestamp))
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@ -16,9 +16,8 @@ _syscalls = {
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"rtio_oe": "ib:n",
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"rtio_set": "Iii:n",
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"rtio_replace": "Iii:n",
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"rtio_sync": "i:n",
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"rtio_get_counter": "n:I",
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"rtio_get": "i:I",
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"rtio_get": "iI:I",
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"rtio_pileup_count": "i:i",
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"dds_phase_clear_en": "ib:n",
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"dds_program": "IiiiIbb:n",
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@ -2,52 +2,156 @@ from fractions import Fraction
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFO
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from migen.genlib.cdc import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from artiqlib.rtio.rbus import get_fine_ts_width
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
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counter_width = flen(counter)
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.value = Signal(2)
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self.writable = Signal()
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self.we = Signal()
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self.replace = Signal()
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self.underflow = Signal()
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self.level = Signal(bits_for(fifo_depth))
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class _GrayCodeTransfer(Module):
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def __init__(self, width):
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self.i = Signal(width) # in rio domain
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self.o = Signal(width) # in rsys domain
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# # #
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# detect underflows
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self.sync += \
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If((self.we & self.writable) | self.replace,
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If(self.timestamp[fine_ts_width:] < counter + 2,
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self.underflow.eq(1))
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)
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# convert to Gray code
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value_gray_rio = Signal(width)
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self.sync.rio += value_gray_rio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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self.specials += [
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NoRetiming(value_gray_rio),
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MultiReg(value_gray_rio, value_gray_sys, "rsys")
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]
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# convert back to binary
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value_sys = Signal(width)
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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for i in reversed(range(width-1)):
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self.comb += value_sys[i].eq(value_sys[i+1] ^ value_gray_sys[i])
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self.sync.rsys += self.o.eq(value_sys)
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class _RTIOCounter(Module):
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def __init__(self, width, loopback_latency):
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self.width = width
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# Timestamp counter in RTIO domain for outputs
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self.o_value_rio = Signal(width)
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# Timestamp counter resynchronized to sys domain
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# Lags behind o_value_rio, monotonic and glitch-free
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self.o_value_sys = Signal(width)
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# Timestamp counter in RTIO domain for inputs,
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# compensated for PHY loopback latency
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self.i_value_rio = Signal(width, reset=2**width-loopback_latency)
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# # #
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self.sync.rio += [
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self.o_value_rio.eq(self.o_value_rio + 1),
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self.i_value_rio.eq(self.i_value_rio + 1)
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]
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gt = _GrayCodeTransfer(width)
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self.submodules += gt
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self.comb += gt.i.eq(self.o_value_rio), self.o_value_sys.eq(gt.o)
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# CHOOSING A GUARD TIME
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#
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# The buffer must be transferred to the FIFO soon enough to account for:
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# * transfer of counter to sys domain: Tio + 2*Tsys + Tsys
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# * guard time detection latency: Tsys
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# * FIFO latency: Tsys + 2*Tio
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# Therefore we must choose:
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# guard_io_cycles > (3*Tio + 5*Tsys)/Tio
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#
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# We are writing to the FIFO from the buffer when the guard time has been
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# reached without checking the FIFO's writable status. If the FIFO is full,
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# this will produce an overflow and the event will be incorrectly discarded.
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#
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# When the FIFO is full, it contains fifo_depth events of strictly increasing
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# timestamps.
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#
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# Thus the overflow-causing event's timestamp must satisfy:
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# timestamp*Tio > fifo_depth*Tio + time
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# We also have (guard time reached):
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# timestamp*Tio < time + guard_io_cycles*Tio
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# [NB: time > counter.o_value_sys*Tio]
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# Thus we must have:
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# guard_io_cycles > fifo_depth
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#
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# We can prevent overflows by choosing instead:
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# guard_io_cycles < fifo_depth
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class _RTIOBankO(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth, guard_io_cycles):
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter.width + fine_ts_width)
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self.value = Signal(2)
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self.writable = Signal()
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self.we = Signal() # maximum throughput 1/2
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self.replace = Signal()
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self.underflow = Signal() # valid 2 cycles after we/replace
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self.underflow_reset = Signal()
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# # #
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signal_underflow = Signal()
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fifos = []
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fifo_layout = [("timestamp", counter.width + fine_ts_width),
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("value", 2)]
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for n, chif in enumerate(rbus):
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fifo = SyncFIFO([
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("timestamp", counter_width+fine_ts_width), ("value", 2)],
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2 if chif.mini else fifo_depth)
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# FIFO
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fifo = RenameClockDomains(AsyncFIFO(fifo_layout, fifo_depth),
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{"write": "rsys", "read": "rio"})
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self.submodules += fifo
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fifos.append(fifo)
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# FIFO replace/write
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# Buffer
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buf_valid = Signal()
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buf_timestamp = Signal(counter.width + fine_ts_width)
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buf_value = Signal(2)
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buf_just_written = Signal()
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# Buffer read and FIFO write
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self.comb += [
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fifo.din.timestamp.eq(self.timestamp),
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fifo.din.value.eq(self.value),
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fifo.we.eq((self.we | self.replace) & (self.sel == n)),
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fifo.replace.eq(self.replace)
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fifo.din.timestamp.eq(buf_timestamp),
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fifo.din.value.eq(buf_value)
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]
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in_guard_time = Signal()
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self.comb += in_guard_time.eq(
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buf_timestamp[fine_ts_width:] < counter.o_value_sys + guard_io_cycles)
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self.sync.rsys += If(in_guard_time, buf_valid.eq(0))
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self.comb += \
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If(buf_valid,
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If(in_guard_time,
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If(buf_just_written,
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signal_underflow.eq(1)
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).Else(
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fifo.we.eq(1)
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)
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),
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If(self.we & (self.sel == n), fifo.we.eq(1))
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)
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# Buffer write
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# Must come after read to handle concurrent read+write properly
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self.sync.rsys += [
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buf_just_written.eq(0),
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If((self.we | self.replace) & (self.sel == n),
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# Replace operations on empty buffers may happen
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# on underflows, which will be correctly reported.
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buf_just_written.eq(1),
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buf_valid.eq(1),
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buf_timestamp.eq(self.timestamp),
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buf_value.eq(self.value)
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)
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]
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# FIFO read
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self.comb += [
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chif.o_stb.eq(fifo.readable &
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(fifo.dout.timestamp[fine_ts_width:] == counter)),
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(fifo.dout.timestamp[fine_ts_width:] == counter.o_value_rio)),
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chif.o_value.eq(fifo.dout.value),
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fifo.re.eq(chif.o_stb)
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]
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@ -55,22 +159,23 @@ class _RTIOBankO(Module):
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self.comb += chif.o_fine_ts.eq(
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fifo.dout.timestamp[:fine_ts_width])
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selfifo = Array(fifos)[self.sel]
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self.comb += [
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self.writable.eq(selfifo.writable),
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self.level.eq(selfifo.level)
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self.comb += \
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self.writable.eq(Array(fifo.writable for fifo in fifos)[self.sel])
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self.sync.rsys += [
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If(self.underflow_reset, self.underflow.eq(0)),
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If(signal_underflow, self.underflow.eq(1))
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]
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class _RTIOBankI(Module):
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def __init__(self, rbus, counter, fine_ts_width, fifo_depth):
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counter_width = flen(counter)
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self.sel = Signal(max=len(rbus))
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self.timestamp = Signal(counter_width+fine_ts_width)
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self.timestamp = Signal(counter.width + fine_ts_width)
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self.value = Signal()
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal()
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self.overflow_reset = Signal()
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self.pileup_count = Signal(16)
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self.pileup_reset = Signal()
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@ -81,22 +186,23 @@ class _RTIOBankI(Module):
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readables = []
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overflows = []
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pileup_counts = []
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fifo_layout = [("timestamp", counter.width+fine_ts_width),
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("value", 1)]
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for n, chif in enumerate(rbus):
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if hasattr(chif, "oe"):
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sensitivity = Signal(2)
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self.sync += If(~chif.oe & chif.o_stb,
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sensitivity.eq(chif.o_value))
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self.sync.rio += If(~chif.oe & chif.o_stb,
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sensitivity.eq(chif.o_value))
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fifo = SyncFIFO([
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("timestamp", counter_width+fine_ts_width), ("value", 1)],
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fifo_depth)
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fifo = RenameClockDomains(AsyncFIFO(fifo_layout, fifo_depth),
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{"read": "rsys", "write": "rio"})
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self.submodules += fifo
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# FIFO write
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if fine_ts_width:
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full_ts = Cat(chif.i_fine_ts, counter)
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full_ts = Cat(chif.i_fine_ts, counter.i_value_rio)
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else:
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full_ts = counter
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full_ts = counter.i_value_rio
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self.comb += [
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fifo.din.timestamp.eq(full_ts),
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fifo.din.value.eq(chif.i_value),
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@ -113,19 +219,35 @@ class _RTIOBankI(Module):
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self.comb += fifo.re.eq(self.re & (self.sel == n))
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overflow = Signal()
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self.sync += If(fifo.we & ~fifo.writable, overflow.eq(1))
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overflows.append(overflow)
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overflow_reset_sync = PulseSynchronizer("rsys", "rio")
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self.submodules += overflow_reset_sync
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self.comb += overflow_reset_sync.i.eq(
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self.overflow_reset & (self.sel == n))
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self.sync.rio += [
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If(overflow_reset_sync.o, overflow.eq(0)),
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If(fifo.we & ~fifo.writable, overflow.eq(1))
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]
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overflow_sys = Signal()
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self.specials += MultiReg(overflow, overflow_sys, "rsys")
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overflows.append(overflow_sys)
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pileup_count = Signal(16)
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self.sync += \
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If(self.pileup_reset & (self.sel == n),
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pileup_count_reset_sync = PulseSynchronizer("rsys", "rio")
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self.submodules += pileup_count_reset_sync
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self.comb += pileup_count_reset_sync.i.eq(
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self.pileup_reset & (self.sel == n))
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self.sync.rio += \
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If(pileup_count_reset_sync.o,
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pileup_count.eq(0)
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).Elif(chif.i_pileup,
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If(pileup_count != 2**16 - 1, # saturate
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pileup_count.eq(pileup_count + 1)
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)
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)
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pileup_counts.append(pileup_count)
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pileup_count_sync = _GrayCodeTransfer(16)
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self.submodules += pileup_count_sync
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self.comb += pileup_count_sync.i.eq(pileup_count)
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pileup_counts.append(pileup_count_sync.o)
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else:
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timestamps.append(0)
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values.append(0)
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@ -143,60 +265,63 @@ class _RTIOBankI(Module):
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=64):
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def __init__(self, phy, clk_freq, counter_width=32,
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ofifo_depth=64, ififo_depth=64,
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guard_io_cycles=20):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Counters
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reset_counter = Signal()
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o_counter = Signal(counter_width, reset=phy.loopback_latency)
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i_counter = Signal(counter_width)
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self.sync += \
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If(reset_counter,
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o_counter.eq(o_counter.reset),
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i_counter.eq(i_counter.reset)
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).Else(
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o_counter.eq(o_counter + 1),
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i_counter.eq(i_counter + 1)
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)
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# Submodules
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self.submodules.bank_o = InsertReset(_RTIOBankO(
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phy.rbus,
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o_counter, fine_ts_width, ofifo_depth))
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self.submodules.bank_i = InsertReset(_RTIOBankI(
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phy.rbus,
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i_counter, fine_ts_width, ofifo_depth))
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self.submodules.counter = _RTIOCounter(
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counter_width, phy.loopback_latency)
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self.submodules.bank_o = _RTIOBankO(
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phy.rbus, self.counter, fine_ts_width, ofifo_depth, guard_io_cycles)
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self.submodules.bank_i = _RTIOBankI(
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phy.rbus, self.counter, fine_ts_width, ofifo_depth)
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# CSRs
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self._r_reset_logic = CSRStorage(reset=1)
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self._r_reset_counter = CSRStorage(reset=1)
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
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self._r_oe = CSR()
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self._r_o_timestamp = CSRStorage(counter_width+fine_ts_width)
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self._r_o_timestamp = CSRStorage(counter_width + fine_ts_width)
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self._r_o_value = CSRStorage(2)
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_replace = CSR()
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self._r_o_underflow = CSRStatus()
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self._r_o_level = CSRStatus(bits_for(ofifo_depth))
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self._r_o_underflow_reset = CSR()
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self._r_i_timestamp = CSRStatus(counter_width+fine_ts_width)
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self._r_i_timestamp = CSRStatus(counter_width + fine_ts_width)
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self._r_i_value = CSRStatus()
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self._r_i_readable = CSRStatus()
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self._r_i_re = CSR()
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self._r_i_overflow = CSRStatus()
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self._r_i_overflow_reset = CSR()
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self._r_i_pileup_count = CSRStatus(16)
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self._r_i_pileup_reset = CSR()
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self._r_counter = CSRStatus(counter_width+fine_ts_width)
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self._r_counter = CSRStatus(counter_width + fine_ts_width)
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self._r_counter_update = CSR()
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self._r_frequency_i = CSRStatus(32)
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self._r_frequency_fn = CSRStatus(8)
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self._r_frequency_fd = CSRStatus(8)
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# Clocking/Reset
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# Create rsys and rio domains based on sys and rio
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# with reset controlled by CSR.
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(self._r_reset.storage)
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio, self._r_reset.storage)
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# OE
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oes = []
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for n, chif in enumerate(phy.rbus):
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@ -212,7 +337,6 @@ class RTIO(Module, AutoCSR):
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# Output/Gate
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self.comb += [
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self.bank_o.reset.eq(self._r_reset_logic.storage),
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self.bank_o.sel.eq(self._r_chan_sel.storage),
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self.bank_o.timestamp.eq(self._r_o_timestamp.storage),
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self.bank_o.value.eq(self._r_o_value.storage),
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|
|
@ -220,28 +344,27 @@ class RTIO(Module, AutoCSR):
|
|||
self.bank_o.we.eq(self._r_o_we.re),
|
||||
self.bank_o.replace.eq(self._r_o_replace.re),
|
||||
self._r_o_underflow.status.eq(self.bank_o.underflow),
|
||||
self._r_o_level.status.eq(self.bank_o.level)
|
||||
self.bank_o.underflow_reset.eq(self._r_o_underflow_reset.re)
|
||||
]
|
||||
|
||||
# Input
|
||||
self.comb += [
|
||||
self.bank_i.reset.eq(self._r_reset_logic.storage),
|
||||
self.bank_i.sel.eq(self._r_chan_sel.storage),
|
||||
self._r_i_timestamp.status.eq(self.bank_i.timestamp),
|
||||
self._r_i_value.status.eq(self.bank_i.value),
|
||||
self._r_i_readable.status.eq(self.bank_i.readable),
|
||||
self.bank_i.re.eq(self._r_i_re.re),
|
||||
self._r_i_overflow.status.eq(self.bank_i.overflow),
|
||||
self.bank_i.overflow_reset.eq(self._r_i_overflow_reset.re),
|
||||
self._r_i_pileup_count.status.eq(self.bank_i.pileup_count),
|
||||
self.bank_i.pileup_reset.eq(self._r_i_pileup_reset.re)
|
||||
]
|
||||
|
||||
# Counter access
|
||||
self.comb += reset_counter.eq(self._r_reset_counter.storage)
|
||||
self.sync += \
|
||||
If(self._r_counter_update.re,
|
||||
self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
|
||||
o_counter))
|
||||
self.counter.o_value_sys))
|
||||
)
|
||||
|
||||
# Frequency
|
||||
|
|
|
|||
|
|
@ -5,25 +5,25 @@ from artiqlib.rtio.rbus import create_rbus
|
|||
|
||||
|
||||
class SimplePHY(Module):
|
||||
def __init__(self, pads, output_only_pads=set(), mini_pads=set()):
|
||||
self.rbus = create_rbus(0, pads, output_only_pads, mini_pads)
|
||||
def __init__(self, pads, output_only_pads=set()):
|
||||
self.rbus = create_rbus(0, pads, output_only_pads)
|
||||
self.loopback_latency = 3
|
||||
|
||||
# # #
|
||||
|
||||
for pad, chif in zip(pads, self.rbus):
|
||||
o_pad = Signal()
|
||||
self.sync += If(chif.o_stb, o_pad.eq(chif.o_value))
|
||||
self.sync.rio += If(chif.o_stb, o_pad.eq(chif.o_value))
|
||||
if hasattr(chif, "oe"):
|
||||
ts = TSTriple()
|
||||
i_pad = Signal()
|
||||
self.sync += ts.oe.eq(chif.oe)
|
||||
self.sync.rio += ts.oe.eq(chif.oe)
|
||||
self.comb += ts.o.eq(o_pad)
|
||||
self.specials += MultiReg(ts.i, i_pad), \
|
||||
ts.get_tristate(pad)
|
||||
|
||||
i_pad_d = Signal()
|
||||
self.sync += i_pad_d.eq(i_pad)
|
||||
self.sync.rio += i_pad_d.eq(i_pad)
|
||||
self.comb += chif.i_stb.eq(i_pad ^ i_pad_d), \
|
||||
chif.i_value.eq(i_pad)
|
||||
else:
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ from migen.fhdl.std import *
|
|||
from migen.genlib.record import Record
|
||||
|
||||
|
||||
def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
|
||||
def create_rbus(fine_ts_bits, pads, output_only_pads):
|
||||
rbus = []
|
||||
for pad in pads:
|
||||
layout = [
|
||||
|
|
@ -11,7 +11,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
|
|||
]
|
||||
if fine_ts_bits:
|
||||
layout.append(("o_fine_ts", fine_ts_bits))
|
||||
if pad not in output_only_pads and pad not in mini_pads:
|
||||
if pad not in output_only_pads:
|
||||
layout += [
|
||||
("oe", 1),
|
||||
("i_stb", 1),
|
||||
|
|
@ -20,9 +20,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads, mini_pads):
|
|||
]
|
||||
if fine_ts_bits:
|
||||
layout.append(("i_fine_ts", fine_ts_bits))
|
||||
chif = Record(layout)
|
||||
chif.mini = pad in mini_pads
|
||||
rbus.append(chif)
|
||||
rbus.append(Record(layout))
|
||||
return rbus
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -8,10 +8,8 @@ long long int previous_fud_end_time;
|
|||
void rtio_init(void)
|
||||
{
|
||||
previous_fud_end_time = 0;
|
||||
rtio_reset_counter_write(1);
|
||||
rtio_reset_logic_write(1);
|
||||
rtio_reset_counter_write(0);
|
||||
rtio_reset_logic_write(0);
|
||||
rtio_reset_write(1);
|
||||
rtio_reset_write(0);
|
||||
}
|
||||
|
||||
void rtio_oe(int channel, int oe)
|
||||
|
|
@ -28,8 +26,7 @@ void rtio_set(long long int timestamp, int channel, int value)
|
|||
while(!rtio_o_writable_read());
|
||||
rtio_o_we_write(1);
|
||||
if(rtio_o_underflow_read()) {
|
||||
rtio_reset_logic_write(1);
|
||||
rtio_reset_logic_write(0);
|
||||
rtio_o_underflow_reset_write(1);
|
||||
exception_raise(EID_RTIO_UNDERFLOW);
|
||||
}
|
||||
}
|
||||
|
|
@ -41,33 +38,25 @@ void rtio_replace(long long int timestamp, int channel, int value)
|
|||
rtio_o_value_write(value);
|
||||
rtio_o_replace_write(1);
|
||||
if(rtio_o_underflow_read()) {
|
||||
rtio_reset_logic_write(1);
|
||||
rtio_reset_logic_write(0);
|
||||
rtio_o_underflow_reset_write(1);
|
||||
exception_raise(EID_RTIO_UNDERFLOW);
|
||||
}
|
||||
}
|
||||
|
||||
void rtio_sync(int channel)
|
||||
{
|
||||
rtio_chan_sel_write(channel);
|
||||
while(rtio_o_level_read() != 0);
|
||||
}
|
||||
|
||||
long long int rtio_get_counter(void)
|
||||
{
|
||||
rtio_counter_update_write(1);
|
||||
return rtio_counter_read();
|
||||
}
|
||||
|
||||
long long int rtio_get(int channel)
|
||||
long long int rtio_get(int channel, long long int time_limit)
|
||||
{
|
||||
long long int r;
|
||||
|
||||
rtio_chan_sel_write(channel);
|
||||
while(rtio_i_readable_read() || (rtio_o_level_read() != 0)) {
|
||||
while(rtio_i_readable_read() || (rtio_get_counter() < time_limit)) {
|
||||
if(rtio_i_overflow_read()) {
|
||||
rtio_reset_logic_write(1);
|
||||
rtio_reset_logic_write(0);
|
||||
rtio_i_overflow_reset_write(1);
|
||||
exception_raise(EID_RTIO_OVERFLOW);
|
||||
}
|
||||
if(rtio_i_readable_read()) {
|
||||
|
|
@ -93,7 +82,7 @@ int rtio_pileup_count(int channel)
|
|||
|
||||
void rtio_fud_sync(void)
|
||||
{
|
||||
rtio_sync(RTIO_FUD_CHANNEL);
|
||||
while(rtio_get_counter() < previous_fud_end_time);
|
||||
}
|
||||
|
||||
void rtio_fud(long long int fud_time)
|
||||
|
|
@ -113,8 +102,7 @@ void rtio_fud(long long int fud_time)
|
|||
rtio_o_value_write(0);
|
||||
rtio_o_we_write(1);
|
||||
if(rtio_o_underflow_read()) {
|
||||
rtio_reset_logic_write(1);
|
||||
rtio_reset_logic_write(0);
|
||||
rtio_o_underflow_reset_write(1);
|
||||
exception_raise(EID_RTIO_UNDERFLOW);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,9 +5,8 @@ void rtio_init(void);
|
|||
void rtio_oe(int channel, int oe);
|
||||
void rtio_set(long long int timestamp, int channel, int value);
|
||||
void rtio_replace(long long int timestamp, int channel, int value);
|
||||
void rtio_sync(int channel);
|
||||
long long int rtio_get_counter(void);
|
||||
long long int rtio_get(int channel);
|
||||
long long int rtio_get(int channel, long long int time_limit);
|
||||
int rtio_pileup_count(int channel);
|
||||
|
||||
void rtio_fud_sync(void);
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@ static const struct symbol syscalls[] = {
|
|||
{"rtio_oe", rtio_oe},
|
||||
{"rtio_set", rtio_set},
|
||||
{"rtio_replace", rtio_replace},
|
||||
{"rtio_sync", rtio_sync},
|
||||
{"rtio_get_counter", rtio_get_counter},
|
||||
{"rtio_get", rtio_get},
|
||||
{"rtio_pileup_count", rtio_pileup_count},
|
||||
|
|
|
|||
|
|
@ -62,9 +62,10 @@ class ARTIQMiniSoC(BaseSoC):
|
|||
rtio_pads.append(fud)
|
||||
self.submodules.rtiophy = rtio.phy.SimplePHY(
|
||||
rtio_pads,
|
||||
output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3]},
|
||||
mini_pads={fud})
|
||||
output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3], fud})
|
||||
self.submodules.rtio = rtio.RTIO(self.rtiophy, self.clk_freq)
|
||||
self.clock_domains.cd_rtio = ClockDomain()
|
||||
self.comb += self.cd_rtio.clk.eq(ClockSignal())
|
||||
|
||||
if with_test_gen:
|
||||
self.submodules.test_gen = _TestGen(platform.request("ttl", 4))
|
||||
|
|
|
|||
Loading…
Reference in New Issue