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https://github.com/m-labs/artiq.git
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get frequency from RTIO, support fractional frequencies
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@ -3,9 +3,9 @@ import termios
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import struct
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import zlib
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from enum import Enum
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from fractions import Fraction
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import logging
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from artiq.language import units
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from artiq.language import core as core_language
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from artiq.devices.runtime import Environment
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from artiq.devices import runtime_exceptions
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@ -123,9 +123,11 @@ class CoreCom:
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runtime_id += chr(reply)
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if runtime_id != "AROR":
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raise UnsupportedDevice("Unsupported runtime ID: "+runtime_id)
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(ref_period, ) = struct.unpack(">l", _read_exactly(self.port, 4))
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logger.debug("Environment ref_period: {}".format(ref_period))
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return Environment(ref_period*units.ps)
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(ref_freq_i, ref_freq_fn, ref_freq_fd) = struct.unpack(
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">lBB", _read_exactly(self.port, 6))
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ref_period = 1/(ref_freq_i + Fraction(ref_freq_fn, ref_freq_fd))
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logger.debug("environment ref_period: {}".format(ref_period))
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return Environment(ref_period)
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def load(self, kcode):
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_write_exactly(self.port, struct.pack(
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@ -40,4 +40,4 @@ class _UnitsLowerer(ast.NodeTransformer):
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def lower_units(func_def, ref_period):
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_UnitsLowerer(ref_period.amount).visit(func_def)
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_UnitsLowerer(ref_period).visit(func_def)
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@ -1,3 +1,5 @@
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from fractions import Fraction
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFO
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@ -138,7 +140,7 @@ class _RTIOBankI(Module):
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class RTIO(Module, AutoCSR):
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def __init__(self, phy, counter_width=32, ofifo_depth=64, ififo_depth=64):
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def __init__(self, phy, clk_freq, counter_width=32, ofifo_depth=64, ififo_depth=64):
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fine_ts_width = get_fine_ts_width(phy.rbus)
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# Submodules
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@ -173,12 +175,9 @@ class RTIO(Module, AutoCSR):
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self._r_counter = CSRStatus(counter_width+fine_ts_width)
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self._r_counter_update = CSR()
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# Counter
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self.sync += \
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If(self._r_counter_update.re,
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self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
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self.bank_o.counter))
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)
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self._r_frequency_i = CSRStatus(32)
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self._r_frequency_fn = CSRStatus(8)
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self._r_frequency_fd = CSRStatus(8)
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# OE
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oes = []
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@ -217,3 +216,20 @@ class RTIO(Module, AutoCSR):
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self._r_i_error.status.eq(
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Cat(self.bank_i.overflow, self.bank_i.pileup))
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]
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# Counter
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self.sync += \
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If(self._r_counter_update.re,
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self._r_counter.status.eq(Cat(Replicate(0, fine_ts_width),
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self.bank_o.counter))
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)
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# Frequency
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clk_freq = Fraction(clk_freq).limit_denominator(255)
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clk_freq_i = int(clk_freq)
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clk_freq_f = clk_freq - clk_freq_i
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self.comb += [
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self._r_frequency_i.status.eq(clk_freq_i),
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self._r_frequency_fn.status.eq(clk_freq_f.numerator),
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self._r_frequency_fd.status.eq(clk_freq_f.denominator)
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]
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@ -154,7 +154,9 @@ void corecom_serve(object_loader load_object, kernel_runner run_kernel)
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if(msgtype == MSGTYPE_REQUEST_IDENT) {
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send_char(MSGTYPE_IDENT);
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send_int(0x41524f52); /* "AROR" - ARTIQ runtime on OpenRISC */
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send_int(1000000000000LL/identifier_frequency_read()); /* RTIO clock period in picoseconds */
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send_int(rtio_frequency_i_read());
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send_char(rtio_frequency_fn_read());
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send_char(rtio_frequency_fd_read());
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} else if(msgtype == MSGTYPE_LOAD_OBJECT)
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receive_and_load_object(load_object);
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else if(msgtype == MSGTYPE_RUN_KERNEL)
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@ -61,7 +61,7 @@ class ARTIQMiniSoC(BaseSoC):
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rtio_pads,
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output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3]},
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mini_pads={fud})
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self.submodules.rtio = rtio.RTIO(self.rtiophy)
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self.submodules.rtio = rtio.RTIO(self.rtiophy, self.clk_freq)
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if with_test_gen:
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self.submodules.test_gen = _TestGen(platform.request("ttl", 4))
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