M-Labs/artiq
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Remove one RTIO out channel to free up some space for travis builds to succeed

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Yann Sionneau 2015-03-19 16:50:14 +01:00 committed by Sebastien Bourdeauducq
parent 3108ffeef6
commit e9092edb98
1 changed files with 1 additions and 1 deletions
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soc/targets/artiq_ppro.py
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@ -111,7 +111,7 @@ class ARTIQMiniSoC(BaseSoC):
platform.request("ttl_h_tx_en").eq(1)
]
rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud]
self.submodules.rtiocrg = _RTIOMiniCRG(platform)
self.submodules.rtiophy = rtio.phy.SimplePHY(