M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-29 05:03:34 +08:00
Code Issues Projects Releases Wiki Activity

kc705: 16 TTLs

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2015-04-03 15:57:25 +08:00
parent fb91955260
commit 5f7161a7de
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
soc/targets/artiq_kc705.py
View File

@ -90,7 +90,7 @@ class _ARTIQSoCPeripherals(BaseSoC):
platform.request("ttl_h_tx_en").eq(1)
]
rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
rtio_outs = [platform.request("ttl", i) for i in range(16)] + [fud]
self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
self.submodules.rtiophy = rtio.phy.SimplePHY(