M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

more PEP8

This commit is contained in:
Sebastien Bourdeauducq 2014-09-05 17:06:41 +08:00
parent 86193437f5
commit 8d7591dfcf
4 changed files with 35 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
soc/artiqlib/ad9858/__init__.py
View File

@ -12,7 +12,7 @@ class AD9858(Module):
Data is zero-padded.
Write to address 64 to pulse the FUD signal.
Address 65 is a GPIO register that controls the sel, p and reset signals.
Address 65 is a GPIO register that controls the sel, p and reset signals.
sel is mapped to the lower bits, followed by p and reset.
Write timing:
@ -55,9 +55,9 @@ class AD9858(Module):
gpio_load = Signal()
self.sync += If(gpio_load, gpio.eq(bus.dat_w))
self.comb += [
Cat(pads.sel, pads.p).eq(gpio),
pads.rst_n.eq(~gpio[-1]),
]
Cat(pads.sel, pads.p).eq(gpio),
pads.rst_n.eq(~gpio[-1]),
]
bus_r_gpio = Signal()
self.comb += If(bus_r_gpio,
@ -193,7 +193,8 @@ class _TB(Module):
pads = _TestPads()
self.submodules.dut = AD9858(pads)
self.submodules.initiator = wishbone.Initiator(_test_gen())
self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.initiator.bus, self.dut.bus)
self.submodules.interconnect = wishbone.InterconnectPointToPoint(
self.initiator.bus, self.dut.bus)
if __name__ == "__main__":

33
soc/artiqlib/rtio/core.py
View File

@ -1,13 +1,13 @@
from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.fifo import SyncFIFOBuffered
from migen.genlib.cdc import MultiReg
from artiqlib.rtio.rbus import get_fine_ts_width
class _RTIOBankO(Module):
def __init__(self, rbus, counter_width, fine_ts_width, fifo_depth, counter_init):
def __init__(self, rbus, counter_width, fine_ts_width,
fifo_depth, counter_init):
self.sel = Signal(max=len(rbus))
self.timestamp = Signal(counter_width+fine_ts_width)
self.value = Signal(2)
@ -22,7 +22,8 @@ class _RTIOBankO(Module):
self.sync += [
counter.eq(counter + 1),
If(self.we & self.writable,
If(self.timestamp[fine_ts_width:] < counter + 2, self.underflow.eq(1))
If(self.timestamp[fine_ts_width:] < counter + 2,
self.underflow.eq(1))
)
]
@ -49,10 +50,14 @@ class _RTIOBankO(Module):
fifo.re.eq(chif.o_stb)
]
if fine_ts_width:
self.comb += chif.o_fine_ts.eq(fifo.dout.timestamp[:fine_ts_width])
self.comb += chif.o_fine_ts.eq(
fifo.dout.timestamp[:fine_ts_width])
selfifo = Array(fifos)[self.sel]
self.comb += self.writable.eq(selfifo.writable), self.level.eq(selfifo.level)
self.comb += [
self.writable.eq(selfifo.writable),
self.level.eq(selfifo.level)
]
class _RTIOBankI(Module):
@ -83,7 +88,7 @@ class _RTIOBankI(Module):
("timestamp", counter_width+fine_ts_width), ("value", 1)],
fifo_depth)
self.submodules += fifo
# FIFO write
if fine_ts_width:
full_ts = Cat(chif.i_fine_ts, counter)
@ -92,8 +97,10 @@ class _RTIOBankI(Module):
self.comb += [
fifo.din.timestamp.eq(full_ts),
fifo.din.value.eq(chif.i_value),
fifo.we.eq(~chif.oe & chif.i_stb &
((chif.i_value & sensitivity[0]) | (~chif.i_value & sensitivity[1])))
fifo.we.eq(
~chif.oe & chif.i_stb &
((chif.i_value & sensitivity[0])
| (~chif.i_value & sensitivity[1])))
]
# FIFO read
@ -101,7 +108,7 @@ class _RTIOBankI(Module):
values.append(fifo.dout.value)
readables.append(fifo.readable)
self.comb += fifo.re.eq(self.re & (self.sel == n))
overflow = Signal()
self.sync += If(fifo.we & ~fifo.writable, overflow.eq(1))
overflows.append(overflow)
@ -124,16 +131,18 @@ class RTIO(Module, AutoCSR):
fine_ts_width = get_fine_ts_width(phy.rbus)
# Submodules
self.submodules.bank_o = InsertReset(_RTIOBankO(phy.rbus,
self.submodules.bank_o = InsertReset(_RTIOBankO(
phy.rbus,
counter_width, fine_ts_width, ofifo_depth,
phy.loopback_latency))
self.submodules.bank_i = InsertReset(_RTIOBankI(phy.rbus,
self.submodules.bank_i = InsertReset(_RTIOBankI(
phy.rbus,
counter_width, fine_ts_width, ofifo_depth))
# CSRs
self._r_reset = CSRStorage(reset=1)
self._r_chan_sel = CSRStorage(flen(self.bank_o.sel))
self._r_oe = CSR()
self._r_o_timestamp = CSRStorage(counter_width+fine_ts_width)

2
soc/artiqlib/rtio/rbus.py
View File

@ -1,6 +1,7 @@
from migen.fhdl.std import *
from migen.genlib.record import Record
def create_rbus(fine_ts_bits, pads, output_only_pads):
rbus = []
for pad in pads:
@ -21,6 +22,7 @@ def create_rbus(fine_ts_bits, pads, output_only_pads):
rbus.append(Record(layout))
return rbus
def get_fine_ts_width(rbus):
if hasattr(rbus[0], "o_fine_ts"):
return flen(rbus[0].o_fine_ts)

8
soc/targets/artiq.py
View File

@ -6,6 +6,7 @@ from targets.ppro import BaseSoC
from artiqlib import rtio, ad9858
_tester_io = [
("user_led", 1, Pins("B:7"), IOStandard("LVTTL")),
("ttl", 0, Pins("C:13"), IOStandard("LVTTL")),
@ -25,6 +26,7 @@ _tester_io = [
IOStandard("LVTTL")),
]
class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 10
@ -35,12 +37,14 @@ class ARTIQMiniSoC(BaseSoC):
BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
platform.add_extension(_tester_io)
self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", 0),
self.submodules.leds = gpio.GPIOOut(Cat(
platform.request("user_led", 0),
platform.request("user_led", 1)))
self.comb += platform.request("ttl_tx_en").eq(1)
rtio_pads = [platform.request("ttl", i) for i in range(4)]
self.submodules.rtiophy = rtio.phy.SimplePHY(rtio_pads,
self.submodules.rtiophy = rtio.phy.SimplePHY(
rtio_pads,
{rtio_pads[1], rtio_pads[2], rtio_pads[3]})
self.submodules.rtio = rtio.RTIO(self.rtiophy)