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targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
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@ -32,11 +32,7 @@ When plugged to a QC-DAQ LVDS adapter, the AD9858 DDS hardware can be used in ad
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+--------------+----------+-----------------+
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| 7 | TTL5 | Output only |
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+--------------+----------+-----------------+
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| 8 | TTL6 | Output only |
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+--------------+----------+-----------------+
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| 9 | TTL7 | Output only |
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+--------------+----------+-----------------+
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| 10 | FUD | DDS driver only |
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| 8 | FUD | DDS driver only |
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+--------------+----------+-----------------+
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The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Papilio Pro board), the corresponding pins on the Papilio Pro can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
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@ -95,7 +95,7 @@ int rtio_pileup_count(int channel)
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return r;
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}
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#define RTIO_FUD_CHANNEL 10
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#define RTIO_FUD_CHANNEL 8
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void rtio_fud_sync(void)
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{
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@ -92,7 +92,7 @@ class ARTIQMiniSoC(BaseSoC):
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(8)] + [fud]
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rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
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self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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