2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00

soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC

This commit is contained in:
Sebastien Bourdeauducq 2014-10-21 18:40:08 +08:00
parent 61a50ee53c
commit 346cca9e90

View File

@ -41,7 +41,7 @@ class _TestGen(Module):
class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 10
"rtio": 12
}
csr_map.update(BaseSoC.csr_map)