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pipistrello: basesoc, cleanup
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parent
4c10182c9f
commit
6217cf5392
@ -30,21 +30,14 @@ class _RTIOCRG(Module, AutoCSR):
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i_FREEZEDCM=0,
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i_RST=ResetSignal())
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rtio_external_clk = platform.request("dds_clock")
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platform.add_period_constraint(rtio_external_clk, 8.0)
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self.rtio_external_clk = platform.request("dds_clock")
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platform.add_period_constraint(self.rtio_external_clk, 8.0)
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self.specials += Instance("BUFGMUX",
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i_I0=rtio_internal_clk,
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i_I1=rtio_external_clk,
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i_I1=self.rtio_external_clk,
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i_S=self._clock_sel.storage,
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o_O=self.cd_rtio.clk)
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platform.add_platform_command("""
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NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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""", rtio_clk=rtio_internal_clk)
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class _Peripherals(BaseSoC):
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csr_map = {
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@ -53,8 +46,8 @@ class _Peripherals(BaseSoC):
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}
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"dds": 0x50000000, # (shadow @0xd0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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@ -107,6 +100,12 @@ class _Peripherals(BaseSoC):
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self.submodules.rtiocrg = _RTIOCRG(platform)
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self.submodules.rtio = rtio.RTIO(rtio_channels,
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clk_freq=125000000)
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platform.add_platform_command("""
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NET "{rtio_ext_clk}" TNM_NET = "GRPrtio_ext_clk";
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NET "{sys_clk}" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPrtio_ext_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_ext_clk" TIG;
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""", rtio_ext_clk=self.rtiocrg.rtio_external_clk, sys_clk=self.crg.cd_sys.clk)
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dds_pads = platform.request("dds")
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self.submodules.dds = ad9858.AD9858(dds_pads)
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@ -120,18 +119,20 @@ class UP(_Peripherals):
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
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rtio_csrs)
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self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_Peripherals.csr_map)
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mem_map = {
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(_Peripherals.mem_map)
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@ -141,16 +142,21 @@ class AMP(_Peripherals):
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i2)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
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self.rtiowb.bus)
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self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
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rtio_csrs)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
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self.kernel_cpu.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
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self.dds.bus)
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self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
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default_subtarget = UP
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