M-Labs/artiq
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adapt code to MiSoC's changes

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Florent Kermarrec 2015-02-28 12:37:12 +01:00 committed by Sebastien Bourdeauducq
parent f307897bec
commit 9cf8db2f14
2 changed files with 3 additions and 2 deletions
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2
soc/targets/artiq_kc705.py
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@ -3,7 +3,7 @@ from migen.bank.description import *
from migen.bank import wbgen
from mibuild.generic_platform import *
from misoclib import gpio
from misoclib.cpu.peripherals import gpio
from targets.kc705 import BaseSoC
from artiqlib import rtio, ad9858

3
soc/targets/artiq_ppro.py
View File

@ -3,7 +3,7 @@ from migen.bank.description import *
from migen.bank import wbgen
from mibuild.generic_platform import *
from misoclib import gpio
from misoclib.cpu.peripherals import gpio
from targets.ppro import BaseSoC
from artiqlib import rtio, ad9858
@ -96,6 +96,7 @@ class ARTIQMiniSoC(BaseSoC):
with_test_gen=False, **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type, ramcon_type=ramcon_type,
with_l2=with_l2,
**kwargs)
platform.add_extension(_tester_io)