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artiq
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soc/target: use only 8 TTL channels for now

This commit is contained in:
Sebastien Bourdeauducq 2014-07-20 18:38:41 -06:00
parent 9b5c28af82
commit ede3667fd3
1 changed files with 1 additions and 1 deletions
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soc/targets/artiq.py
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@ -104,6 +104,6 @@ class ARTIQSoC(SDRAMSoC):
self.register_rom(self.spiflash.bus)
self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(16)])
self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(8)])
default_subtarget = ARTIQSoC