 Jack-Zheng
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66d7d68a55
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CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
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2021-07-09 20:18:06 +08:00 |
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Jack-Zheng
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3dd53b1fe4
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PCB: refill polygon
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2021-07-09 16:19:37 +08:00 |
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Jack-Zheng
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3a06817165
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CurrentSense: connect FAULT signal to MCU
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2021-07-09 16:07:40 +08:00 |
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Jack-Zheng
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191eacdf8c
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HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout; LVDS&IO: fix name issue
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2021-07-09 14:36:13 +08:00 |
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Jack-Zheng
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f9574a2098
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HSADC: reselect new op amp
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2021-07-07 17:26:54 +08:00 |
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Jack-Zheng
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3228e16c8f
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MCU, FPGA, Ethernet, PCB: fix decoupling capacitors
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2021-07-07 16:14:10 +08:00 |
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Jack-Zheng
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90053d4887
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PowerSupply: fix TVS protection bug; PCB: finish routing
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2021-07-06 15:41:17 +08:00 |
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Jack-Zheng
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eceba52792
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PCB & FPGA & MCU: fix LVDS impedance issues
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2021-07-06 10:28:18 +08:00 |
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Jack-Zheng
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1b592eed37
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FPGA & MCU & PCB: add decoupling capactors
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2021-07-02 11:04:53 +08:00 |
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Jack-Zheng
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f796eedc08
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PCB: fix grand dead zones
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2021-06-30 15:24:25 +08:00 |
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Jack-Zheng
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4853b02184
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PCB: replace 0201 resistors to 0402 as JLC cannot do SMT for 0201
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2021-06-30 14:59:13 +08:00 |
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Jack-Zheng
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93ba0cbe9d
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HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout
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2021-06-30 14:51:30 +08:00 |
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Jack-Zheng
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17127387c9
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PCB: optimize buck converter and shunt resistor layout
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2021-06-30 11:36:53 +08:00 |
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Jack-Zheng
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26d727f8c5
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PCB: replace LVDS resistors with 0201 package, optimize LVDS pairs layout
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2021-06-29 16:49:26 +08:00 |
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Jack-Zheng
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8ffd698079
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PCB: optimize HSADC layout
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2021-06-29 10:38:12 +08:00 |
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Jack-Zheng
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6584f44f2a
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PCB: fix GND polygon dead zones; all: export BOM
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2021-06-29 10:26:02 +08:00 |
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Jack-Zheng
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10818a4771
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PCB: fix small LVDS connection issue
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2021-06-28 15:49:33 +08:00 |
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Jack-Zheng
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a16bee581b
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PCB: fix small LVDS connection issue
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2021-06-28 15:45:06 +08:00 |
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Jack-Zheng
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185f9eacda
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PCB: finish routing
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2021-06-28 15:40:16 +08:00 |
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Jack-Zheng
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53accc8761
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PCB: finish IO and analog connectors
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2021-06-28 10:40:21 +08:00 |
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Jack-Zheng
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4b15f466a0
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PCB: finish SWD, IIC
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2021-06-25 18:15:56 +08:00 |
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Jack-Zheng
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0e1120d266
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FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing
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2021-06-25 16:57:46 +08:00 |
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Jack-Zheng
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2a31c8b3f3
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PCB: finish LVDS routing
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2021-06-24 15:43:31 +08:00 |
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Jack-Zheng
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37941bfc2c
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PCB: finalize component positions and define board shape
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2021-06-22 17:14:32 +08:00 |
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Jack-Zheng
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6535ff5423
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LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
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2021-06-22 16:34:02 +08:00 |
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Jack-Zheng
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1df738664f
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all: update gitignore; remove redundant files
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2021-06-22 09:44:50 +08:00 |
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Jack-Zheng
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b740887ac2
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HighSpeedADC: fix chip rotation bug, remove SMA connector; all: fix BJT base resistors; Power: remove DC jack; LVDS&IO: replace IDC header with dupont
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2021-06-21 17:06:36 +08:00 |
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Jack-Zheng
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982fefd6b5
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all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
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2021-06-21 16:05:17 +08:00 |
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Jack-Zheng
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327abdeb24
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CurrentSensor: fix bugs and replace opamp with current senser
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2021-06-21 15:10:25 +08:00 |
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Jack-Zheng
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9bcc9a229b
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TestAutomation: replace messy wires with bus
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2021-06-21 12:10:31 +08:00 |
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Jack-Zheng
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45940c1ac8
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all: finish routing
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2021-06-18 16:13:42 +08:00 |
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Jack-Zheng
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9c10edde19
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CurrentSensor: add mid point voltage reference; FPGA: fix pinout
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2021-06-18 14:24:15 +08:00 |
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Jack-Zheng
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0cebd6ed2b
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LVDS: add LVDS ports; all: add LEDs
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2021-06-18 11:30:16 +08:00 |
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Jack-Zheng
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74f4fc201a
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FPGA: add GPIO and ADC parallel port
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2021-06-18 10:27:05 +08:00 |
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Jack-Zheng
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9a62476f9e
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MCU: finish connectors
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2021-06-17 17:33:12 +08:00 |
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Jack-Zheng
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4123caa996
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all: add gitignore; remove redundant files from repo; optimize file name style
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2021-06-17 15:49:24 +08:00 |
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Jack-Zheng
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6cee2d0419
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Current_Senser: add current sampling; all: optimize +3.3VA
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2021-06-17 15:30:51 +08:00 |
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Jack-Zheng
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9f7ffb7754
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docs: remove unused Chinese docs
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2021-06-17 11:12:40 +08:00 |
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Jack-Zheng
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dfe4255a21
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MCU: finish FSMC, PWM
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2021-06-17 10:52:33 +08:00 |
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Jack-Zheng
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fc8c667020
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Power: fix hierarchical and global label
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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5b4801ff74
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FPGA: finish EEM, I2C, CFG, SPI FLASH
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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fc2cb47610
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all: map symbol and footpins
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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24471104a5
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Analog_LVDS: finish ADC
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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66188cd3ad
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Ethernet: finish ethernet controller and PoE input
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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e28d01d115
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PowerSupply: finish power supply part: 12V --(DCDC)--> 6.5V --(LDO)--> 5V+3.3V+2.5V+1.2V
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2021-06-16 17:32:33 +08:00 |
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Jack-Zheng
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83bc618f77
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PowerSupply: finish PoE and 12V input schematic
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2021-06-16 17:32:32 +08:00 |
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Jack-Zheng
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232af06c28
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components confirmed; datasheet collected; framework finished
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2021-06-16 17:32:32 +08:00 |
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Jack-Zheng
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da19dad9cd
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init project
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2021-06-16 17:31:36 +08:00 |