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PCB & FPGA & MCU: fix LVDS impedance issues

This commit is contained in:
Jack-Zheng 2021-07-06 10:28:18 +08:00
parent 1b592eed37
commit eceba52792
4 changed files with 12254 additions and 11561 deletions
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166
FPGA.sch
View File

@ -158,18 +158,14 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 1160 695
1 1100 6950
1 0 0 -1
$EndComp
Text Label 3800 3700 0 50 ~ 0
Text Label 3800 4800 0 50 ~ 0
I2C_0_SDA
Text Label 3800 3400 0 50 ~ 0
Text Label 3800 3500 0 50 ~ 0
I2C_0_SCL
Text Label 3800 4300 0 50 ~ 0
Text Label 3800 5100 0 50 ~ 0
I2C_1_SDA
Text Label 3800 3900 0 50 ~ 0
Text Label 3800 4600 0 50 ~ 0
I2C_1_SCL
Text Label 3800 4900 0 50 ~ 0
I2C_2_SDA
Text Label 3800 4700 0 50 ~ 0
I2C_2_SCL
$Comp
L Power_Protection:PRTR5V0U2X D2
U 1 1 6137EFAD
@ -200,30 +196,22 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 3360 695
1 3300 6950
1 0 0 -1
$EndComp
Text HLabel 3850 3700 2 50 Input ~ 0
Text HLabel 3850 4800 2 50 Input ~ 0
FPGA_EEM0_IIC_SDA
Text HLabel 3850 3400 2 50 Input ~ 0
Text HLabel 3850 3500 2 50 Input ~ 0
FPGA_EEM0_IIC_SCL
Text HLabel 3850 4300 2 50 Input ~ 0
Text HLabel 3850 5100 2 50 Input ~ 0
FPGA_EEM1_IIC_SDA
Text HLabel 3850 3900 2 50 Input ~ 0
Text HLabel 3850 4600 2 50 Input ~ 0
FPGA_EEM1_IIC_SCL
Text HLabel 3850 4900 2 50 Input ~ 0
FPGA_EEM2_IIC_SDA
Text HLabel 3850 4700 2 50 Input ~ 0
FPGA_EEM2_IIC_SCL
Wire Wire Line
3750 3700 3850 3700
3750 4800 3850 4800
Wire Wire Line
3750 3400 3850 3400
3750 3500 3850 3500
Wire Wire Line
3750 4300 3850 4300
3750 5100 3850 5100
Wire Wire Line
3750 3900 3850 3900
Wire Wire Line
3750 4900 3850 4900
Wire Wire Line
3750 4700 3850 4700
3750 4600 3850 4600
Wire Wire Line
1100 6400 1100 6450
Wire Wire Line
@ -2495,9 +2483,7 @@ Wire Wire Line
8150 3900 8300 3900
Wire Wire Line
8150 4000 8300 4000
NoConn ~ 3750 4800
NoConn ~ 3750 5000
NoConn ~ 3750 5100
NoConn ~ 3750 5200
NoConn ~ 3750 5400
NoConn ~ 3750 5500
@ -2518,93 +2504,93 @@ Text Label 7750 5100 0 50 ~ 0
LVDS0_1_N
Text Label 7750 5200 0 50 ~ 0
LVDS0_1_P
Text Label 7750 4700 0 50 ~ 0
LVDS0_2_N
Text Label 7750 4800 0 50 ~ 0
LVDS0_2_P
Text Label 7750 4300 0 50 ~ 0
LVDS0_3_N
Text Label 7750 4400 0 50 ~ 0
LVDS0_3_P
Text Label 7750 3300 0 50 ~ 0
LVDS0_4_N
Text Label 7750 3400 0 50 ~ 0
LVDS0_4_P
Text Label 7750 3100 0 50 ~ 0
LVDS0_5_N
LVDS0_2_N
Text Label 7750 3200 0 50 ~ 0
LVDS0_5_P
LVDS0_2_P
Text Label 7750 4700 0 50 ~ 0
LVDS0_3_N
Text Label 7750 4800 0 50 ~ 0
LVDS0_3_P
Text Label 7750 2700 0 50 ~ 0
LVDS0_6_N
LVDS0_4_N
Text Label 7750 2800 0 50 ~ 0
LVDS0_6_P
LVDS0_4_P
Text Label 7750 4300 0 50 ~ 0
LVDS0_5_N
Text Label 7750 4400 0 50 ~ 0
LVDS0_5_P
Text Label 7750 2100 0 50 ~ 0
LVDS0_7_N
LVDS0_6_N
Text Label 7750 2200 0 50 ~ 0
LVDS0_6_P
Text Label 7750 3300 0 50 ~ 0
LVDS0_7_N
Text Label 7750 3400 0 50 ~ 0
LVDS0_7_P
Text Label 7750 3900 0 50 ~ 0
LVDS1_1_N
Text Label 7750 4000 0 50 ~ 0
LVDS1_1_P
Text Label 7750 3700 0 50 ~ 0
LVDS1_2_N
Text Label 7750 3800 0 50 ~ 0
LVDS1_2_P
Text Label 7750 2900 0 50 ~ 0
LVDS1_3_N
Text Label 7750 3000 0 50 ~ 0
LVDS1_3_P
Text Label 7750 1100 0 50 ~ 0
LVDS1_7_N
Text Label 7750 1200 0 50 ~ 0
LVDS1_7_P
Text Label 7750 5900 0 50 ~ 0
LVDS2_0_N
Text Label 7750 6000 0 50 ~ 0
LVDS2_0_P
Text Label 7750 5700 0 50 ~ 0
LVDS2_1_N
LVDS1_1_N
Text Label 7750 5800 0 50 ~ 0
LVDS2_1_P
LVDS1_1_P
Text Label 7750 4900 0 50 ~ 0
LVDS2_2_N
LVDS1_2_N
Text Label 7750 5000 0 50 ~ 0
LVDS2_2_P
LVDS1_2_P
Text Label 7750 4500 0 50 ~ 0
LVDS2_3_N
LVDS1_3_N
Text Label 7750 4600 0 50 ~ 0
LVDS2_3_P
LVDS1_3_P
Text Label 7750 3500 0 50 ~ 0
LVDS2_4_N
LVDS1_7_N
Text Label 7750 3600 0 50 ~ 0
LVDS2_4_P
LVDS1_7_P
Text Label 7750 2900 0 50 ~ 0
LVDS2_0_N
Text Label 7750 3000 0 50 ~ 0
LVDS2_0_P
Text Label 7750 2300 0 50 ~ 0
LVDS2_5_N
LVDS2_1_N
Text Label 7750 2400 0 50 ~ 0
LVDS2_1_P
Text Label 7750 1700 0 50 ~ 0
LVDS2_2_N
Text Label 7750 1800 0 50 ~ 0
LVDS2_2_P
Text Label 7750 1900 0 50 ~ 0
LVDS2_3_N
Text Label 7750 2000 0 50 ~ 0
LVDS2_3_P
Text Label 7750 1500 0 50 ~ 0
LVDS2_4_N
Text Label 7750 1600 0 50 ~ 0
LVDS2_4_P
Text Label 7750 1300 0 50 ~ 0
LVDS2_5_N
Text Label 7750 1400 0 50 ~ 0
LVDS2_5_P
Text Label 7750 2500 0 50 ~ 0
LVDS2_6_N
Text Label 7750 2600 0 50 ~ 0
LVDS2_6_P
Text Label 7750 1900 0 50 ~ 0
Text Label 7750 1100 0 50 ~ 0
LVDS2_7_N
Text Label 7750 2000 0 50 ~ 0
Text Label 7750 1200 0 50 ~ 0
LVDS2_7_P
Text Label 7750 4100 0 50 ~ 0
Text Label 7750 5900 0 50 ~ 0
LVDS1_0_N
Text Label 7750 4200 0 50 ~ 0
Text Label 7750 6000 0 50 ~ 0
LVDS1_0_P
Text Label 7750 1400 0 50 ~ 0
Text Label 7750 3800 0 50 ~ 0
LVDS1_6_P
Text Label 7750 1300 0 50 ~ 0
Text Label 7750 3700 0 50 ~ 0
LVDS1_6_N
Text Label 7750 1600 0 50 ~ 0
Text Label 7750 4000 0 50 ~ 0
LVDS1_5_P
Text Label 7750 1500 0 50 ~ 0
Text Label 7750 3900 0 50 ~ 0
LVDS1_5_N
Text Label 7750 1800 0 50 ~ 0
Text Label 7750 4200 0 50 ~ 0
LVDS1_4_P
Text Label 7750 1700 0 50 ~ 0
Text Label 7750 4100 0 50 ~ 0
LVDS1_4_N
Text HLabel 5850 2500 2 50 Input ~ 0
FPGA_IO0
@ -2666,7 +2652,6 @@ NoConn ~ 1800 5500
NoConn ~ 1800 5700
NoConn ~ 1800 5800
NoConn ~ 1800 5900
NoConn ~ 3750 4600
NoConn ~ 3750 4500
NoConn ~ 3750 4400
NoConn ~ 3750 4200
@ -2674,7 +2659,6 @@ NoConn ~ 3750 4100
NoConn ~ 3750 4000
NoConn ~ 3750 3800
NoConn ~ 3750 3600
NoConn ~ 3750 3500
NoConn ~ 3750 3300
NoConn ~ 3750 3200
NoConn ~ 3750 3100
@ -3254,4 +3238,18 @@ Wire Wire Line
12250 3450 12250 3400
Wire Wire Line
12650 3450 12650 3500
NoConn ~ 3750 3400
NoConn ~ 3750 3700
Text Label 3800 3900 0 50 ~ 0
I2C_2_SDA
Text HLabel 3850 3900 2 50 Input ~ 0
FPGA_EEM2_IIC_SDA
Wire Wire Line
3750 3900 3850 3900
Text Label 3800 4300 0 50 ~ 0
I2C_2_SCL
Text HLabel 3850 4300 2 50 Input ~ 0
FPGA_EEM2_IIC_SCL
Wire Wire Line
3750 4300 3850 4300
$EndSCHEMATC

140
MCU.sch
View File

@ -795,29 +795,29 @@ Text Label 7650 3300 0 50 ~ 0
SPI2_MISO
Text Label 7650 3400 0 50 ~ 0
SPI2_MOSI
Wire Wire Line
8900 3700 8500 3700
Wire Wire Line
8500 3800 8900 3800
Wire Wire Line
8900 3200 8500 3200
Wire Wire Line
8500 3300 8900 3300
Wire Wire Line
8900 3500 8500 3500
8900 3400 8500 3400
Wire Wire Line
8500 3600 8900 3600
Wire Wire Line
8900 3700 8500 3700
Wire Wire Line
8500 3800 8900 3800
Text Label 8550 3500 0 50 ~ 0
PWM1
Text Label 8550 3600 0 50 ~ 0
PWM2
Text Label 8550 3700 0 50 ~ 0
PWM3
Text Label 8550 3800 0 50 ~ 0
PWM4
8500 3500 8900 3500
Text Label 8550 3200 0 50 ~ 0
UART4_TX
PWM1
Text Label 8550 3300 0 50 ~ 0
PWM2
Text Label 8550 3400 0 50 ~ 0
PWM3
Text Label 8550 3500 0 50 ~ 0
PWM4
Text Label 8550 3700 0 50 ~ 0
UART4_TX
Text Label 8550 3800 0 50 ~ 0
UART4_RX
Wire Wire Line
8000 3600 7600 3600
@ -846,7 +846,7 @@ Wire Wire Line
Wire Wire Line
8500 3100 9050 3100
Wire Wire Line
8500 3400 9050 3400
8500 3600 9050 3600
Wire Wire Line
8000 3000 7500 3000
Wire Wire Line
@ -895,12 +895,12 @@ $EndComp
$Comp
L power:GND #PWR0134
U 1 1 613D2703
P 9050 3400
F 0 "#PWR0134" H 9050 3150 50 0001 C CNN
F 1 "GND" V 9055 3272 50 0000 R CNN
F 2 "" H 9050 3400 50 0001 C CNN
F 3 "" H 9050 3400 50 0001 C CNN
1 9050 3400
P 9050 3600
F 0 "#PWR0134" H 9050 3350 50 0001 C CNN
F 1 "GND" V 9055 3472 50 0000 R CNN
F 2 "" H 9050 3600 50 0001 C CNN
F 3 "" H 9050 3600 50 0001 C CNN
1 9050 3600
0 -1 -1 0
$EndComp
$Comp
@ -972,44 +972,42 @@ $EndComp
$Comp
L Device:LED D21
U 1 1 62108C04
P 6450 5150
F 0 "D21" H 6443 4895 50 0000 C CNN
F 1 "LED_CPU" H 6443 4986 50 0000 C CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 6450 5150 50 0001 C CNN
F 3 "~" H 6450 5150 50 0001 C CNN
1 6450 5150
-1 0 0 1
P 6450 5250
F 0 "D21" H 6443 4995 50 0000 C CNN
F 1 "LED_CPU" H 6443 5086 50 0000 C CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 6450 5250 50 0001 C CNN
F 3 "~" H 6450 5250 50 0001 C CNN
1 6450 5250
-1 0 0 -1
$EndComp
$Comp
L Device:R R124
U 1 1 6210A0E7
P 6850 5150
F 0 "R124" V 6643 5150 50 0000 C CNN
F 1 "100" V 6734 5150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 6780 5150 50 0001 C CNN
F 3 "~" H 6850 5150 50 0001 C CNN
1 6850 5150
0 1 1 0
P 6850 5250
F 0 "R124" V 6643 5250 50 0000 C CNN
F 1 "100" V 6734 5250 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 6780 5250 50 0001 C CNN
F 3 "~" H 6850 5250 50 0001 C CNN
1 6850 5250
0 1 -1 0
$EndComp
$Comp
L power:GND #PWR0124
U 1 1 6210B2EE
P 7100 5400
F 0 "#PWR0124" H 7100 5150 50 0001 C CNN
F 1 "GND" H 7105 5227 50 0000 C CNN
F 2 "" H 7100 5400 50 0001 C CNN
F 3 "" H 7100 5400 50 0001 C CNN
1 7100 5400
1 0 0 -1
P 7100 5000
F 0 "#PWR0124" H 7100 4750 50 0001 C CNN
F 1 "GND" H 7105 4827 50 0000 C CNN
F 2 "" H 7100 5000 50 0001 C CNN
F 3 "" H 7100 5000 50 0001 C CNN
1 7100 5000
1 0 0 1
$EndComp
Wire Wire Line
7100 5250 7100 5150
7100 5150 7100 5250
Wire Wire Line
7100 5150 7000 5150
7100 5250 7000 5250
Wire Wire Line
6700 5150 6600 5150
Wire Wire Line
6300 5150 5000 5150
6700 5250 6600 5250
$Comp
L Switch:SW_Push SW2
U 1 1 62CA6A93
@ -1064,12 +1062,10 @@ Connection ~ 3350 1250
Wire Wire Line
3350 1250 3350 1100
Wire Wire Line
5900 5250 5000 5250
6300 5150 7100 5150
Wire Wire Line
6300 5250 7100 5250
Wire Wire Line
7100 5400 7100 5250
Connection ~ 7100 5250
7100 5000 7100 5150
Connection ~ 7100 5150
Text HLabel 5400 6550 2 50 Input ~ 0
CPU_ENC_INT
Text HLabel 5400 4050 2 50 Input ~ 0
@ -1078,12 +1074,12 @@ Text HLabel 5400 6650 2 50 Input ~ 0
CPU_POE_AT_EVENT
Text HLabel 5400 3550 2 50 Input ~ 0
CPU_POE_SRC_STATUS
Wire Wire Line
5400 2550 5000 2550
Wire Wire Line
5000 2850 5400 2850
Wire Wire Line
5400 2950 5000 2950
Wire Wire Line
5000 6350 5400 6350
Wire Wire Line
5400 2850 5000 2850
Wire Wire Line
5400 3550 5000 3550
Wire Wire Line
@ -1092,16 +1088,16 @@ Wire Wire Line
5000 6550 5400 6550
Wire Wire Line
5000 6650 5400 6650
Text HLabel 5400 2550 2 50 Input ~ 0
CPU_FPGA_CSBSEL0
Text HLabel 5400 2950 2 50 Input ~ 0
CPU_FPGA_CSBSEL1
Text HLabel 5400 6350 2 50 Input ~ 0
CPU_FPGA_CDONE
CPU_FPGA_CSBSEL0
Text HLabel 5400 2550 2 50 Input ~ 0
CPU_FPGA_CSBSEL1
Text HLabel 5400 2850 2 50 Input ~ 0
CPU_FPGA_CDONE
Text HLabel 5400 2950 2 50 Input ~ 0
CPU_FPGA_CRESET
Wire Wire Line
5000 2550 5400 2550
5000 6350 5400 6350
NoConn ~ 5000 5350
NoConn ~ 5000 5450
NoConn ~ 3000 5350
@ -1165,13 +1161,13 @@ $EndComp
$Comp
L Switch:SW_Push SW3
U 1 1 62CCB907
P 6100 5250
F 0 "SW3" H 6100 5535 50 0000 C CNN
F 1 "SW_CPU" H 6100 5444 50 0000 C CNN
F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 6100 5450 50 0001 C CNN
F 3 "~" H 6100 5450 50 0001 C CNN
1 6100 5250
-1 0 0 1
P 6100 5150
F 0 "SW3" H 6100 5435 50 0000 C CNN
F 1 "SW_CPU" H 6100 5344 50 0000 C CNN
F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 6100 5350 50 0001 C CNN
F 3 "~" H 6100 5350 50 0001 C CNN
1 6100 5150
-1 0 0 -1
$EndComp
NoConn ~ 8700 2150
NoConn ~ 8700 2250
@ -1397,4 +1393,8 @@ Connection ~ 8800 900
Wire Wire Line
9200 850 9200 900
Connection ~ 9200 900
Wire Wire Line
5900 5150 5000 5150
Wire Wire Line
6300 5250 5000 5250
$EndSCHEMATC

23473
TestAutomation.kicad_pcb
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File diff suppressed because it is too large Load Diff

36
TestAutomation.pro
View File

@ -1,4 +1,4 @@
update=Fri Jun 25 11:54:49 2021
update=Mon Jul 5 11:18:51 2021
version=1
last_client=kicad
[general]
@ -38,7 +38,7 @@ MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.127
TrackWidth1=0.25
TrackWidth1=0.254
TrackWidth2=0.0889
TrackWidth3=0.1016
TrackWidth4=0.127
@ -47,8 +47,8 @@ TrackWidth6=0.508
TrackWidth7=0.762
TrackWidth8=1.016
TrackWidth9=1.27
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter1=0.45
ViaDrill1=0.25
ViaDiameter2=0.4
ViaDrill2=0.2
ViaDiameter3=0.45
@ -257,11 +257,33 @@ Enabled=0
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.0889
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
TrackWidth=0.254
ViaDiameter=0.45
ViaDrill=0.25
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.0889
dPairGap=0.1016
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Diff_In
Clearance=0.0889
TrackWidth=0.1524
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.1143
dPairGap=0.1524
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=Diff_Out
Clearance=0.0889
TrackWidth=0.127
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.127
dPairGap=0.127
dPairViaGap=0.25