|
FabricationOutput
|
PCB: fix GND polygon dead zones; all: export BOM
|
2021-06-29 10:26:02 +08:00 |
|
STM32CubeMx
|
TestAutomation: replace messy wires with bus
|
2021-06-21 12:10:31 +08:00 |
|
TestAutomation.pretty
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
.gitignore
|
all: update gitignore; remove redundant files
|
2021-06-22 09:44:50 +08:00 |
|
CurrentSenser.sch
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
Ethernet.sch
|
CurrentSense: connect FAULT signal to MCU
|
2021-07-09 16:07:40 +08:00 |
|
FPGA.sch
|
CurrentSense: connect FAULT signal to MCU
|
2021-07-09 16:07:40 +08:00 |
|
HighSpeedADC.sch
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
LVDS_IO.sch
|
CurrentSense: connect FAULT signal to MCU
|
2021-07-09 16:07:40 +08:00 |
|
MCU.sch
|
CurrentSense: connect FAULT signal to MCU
|
2021-07-09 16:07:40 +08:00 |
|
Power.sch
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
TestAutomation.bck
|
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
|
2021-06-21 16:05:17 +08:00 |
|
TestAutomation.dcm
|
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
|
2021-06-21 16:05:17 +08:00 |
|
TestAutomation.kicad_pcb
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
TestAutomation.lib
|
HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout; LVDS&IO: fix name issue
|
2021-07-09 14:36:13 +08:00 |
|
TestAutomation.net
|
PCB: finish LVDS routing
|
2021-06-24 15:43:31 +08:00 |
|
TestAutomation.pro
|
HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout; LVDS&IO: fix name issue
|
2021-07-09 14:36:13 +08:00 |
|
TestAutomation.sch
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
fp-lib-table
|
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
|
2021-06-21 16:05:17 +08:00 |
|
sym-lib-table
|
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
|
2021-06-21 16:05:17 +08:00 |
Jack-Zheng
66d7d68a55