PCB: finish SWD, IIC

This commit is contained in:
Jack-Zheng 2021-06-25 18:15:56 +08:00
parent 0e1120d266
commit 4b15f466a0
2 changed files with 5119 additions and 4975 deletions

349
FPGA.sch
View File

@ -158,17 +158,17 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 1160 695
1 1100 6950
1 0 0 -1
$EndComp
Text Label 3850 -400 0 50 ~ 0
Text Label 3800 3700 0 50 ~ 0
I2C_0_SDA
Text Label 3850 -300 0 50 ~ 0
Text Label 3800 3400 0 50 ~ 0
I2C_0_SCL
Text Label 3850 -200 0 50 ~ 0
Text Label 3800 4300 0 50 ~ 0
I2C_1_SDA
Text Label 3850 -100 0 50 ~ 0
Text Label 3800 3900 0 50 ~ 0
I2C_1_SCL
Text Label 3850 0 0 50 ~ 0
Text Label 3800 4900 0 50 ~ 0
I2C_2_SDA
Text Label 3850 100 0 50 ~ 0
Text Label 3800 4700 0 50 ~ 0
I2C_2_SCL
$Comp
L Power_Protection:PRTR5V0U2X D2
@ -200,30 +200,30 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf" H 3360 695
1 3300 6950
1 0 0 -1
$EndComp
Text HLabel 3900 -400 2 50 Input ~ 0
Text HLabel 3850 3700 2 50 Input ~ 0
FPGA_EEM0_IIC_SDA
Text HLabel 3900 -300 2 50 Input ~ 0
Text HLabel 3850 3400 2 50 Input ~ 0
FPGA_EEM0_IIC_SCL
Text HLabel 3900 -200 2 50 Input ~ 0
Text HLabel 3850 4300 2 50 Input ~ 0
FPGA_EEM1_IIC_SDA
Text HLabel 3900 -100 2 50 Input ~ 0
Text HLabel 3850 3900 2 50 Input ~ 0
FPGA_EEM1_IIC_SCL
Text HLabel 3900 0 2 50 Input ~ 0
Text HLabel 3850 4900 2 50 Input ~ 0
FPGA_EEM2_IIC_SDA
Text HLabel 3900 100 2 50 Input ~ 0
Text HLabel 3850 4700 2 50 Input ~ 0
FPGA_EEM2_IIC_SCL
Wire Wire Line
3800 -400 3900 -400
3750 3700 3850 3700
Wire Wire Line
3800 -300 3900 -300
3750 3400 3850 3400
Wire Wire Line
3800 -200 3900 -200
3750 4300 3850 4300
Wire Wire Line
3800 -100 3900 -100
3750 3900 3850 3900
Wire Wire Line
3800 0 3900 0
3750 4900 3850 4900
Wire Wire Line
3800 100 3900 100
3750 4700 3850 4700
Wire Wire Line
1100 6400 1100 6450
Wire Wire Line
@ -549,14 +549,14 @@ F 3 "~" H 8700 6800 50 0001 C CNN
1 8700 6800
0 1 1 0
$EndComp
Text HLabel 3900 200 2 50 Input ~ 0
Text HLabel 3850 5600 2 50 Input ~ 0
FPGA_IIC_SDA
Text HLabel 3900 300 2 50 Input ~ 0
Text HLabel 3850 5300 2 50 Input ~ 0
FPGA_IIC_SCL
Wire Wire Line
3800 200 3900 200
3750 5600 3850 5600
Wire Wire Line
3800 300 3900 300
3750 5300 3850 5300
Text HLabel 3850 3000 2 50 Input ~ 0
FPGA_ADC_D1
Text HLabel 3850 2900 2 50 Input ~ 0
@ -738,132 +738,132 @@ $EndComp
$Comp
L Device:Q_NPN_BEC Q?
U 1 1 61C9A1CC
P 4250 5700
P 10000 6950
AR Path="/60E3407A/61C9A1CC" Ref="Q?" Part="1"
AR Path="/60C0E996/61C9A1CC" Ref="Q1" Part="1"
F 0 "Q1" H 4440 5746 50 0000 L CNN
F 1 "PMBT3904" H 4440 5655 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-23" H 4450 5800 50 0001 C CNN
F 3 "~" H 4250 5700 50 0001 C CNN
1 4250 5700
1 0 0 -1
F 0 "Q1" H 10190 6996 50 0000 L CNN
F 1 "PMBT3904" H 10190 6905 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-23" H 10200 7050 50 0001 C CNN
F 3 "~" H 10000 6950 50 0001 C CNN
1 10000 6950
0 1 1 0
$EndComp
Wire Wire Line
4050 5400 4050 4600
10300 6750 11100 6750
Wire Wire Line
4050 5600 4050 5700
10100 6750 10000 6750
$Comp
L Device:R_Small R6
U 1 1 623C0DC2
P 4050 5500
F 0 "R6" H 4109 5546 50 0000 L CNN
F 1 "10k" H 4109 5455 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 4050 5500 50 0001 C CNN
F 3 "~" H 4050 5500 50 0001 C CNN
1 4050 5500
1 0 0 -1
P 10200 6750
F 0 "R6" H 10259 6796 50 0000 L CNN
F 1 "10k" H 10259 6705 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 10200 6750 50 0001 C CNN
F 3 "~" H 10200 6750 50 0001 C CNN
1 10200 6750
0 1 1 0
$EndComp
$Comp
L Device:R_Small R9
U 1 1 61ED30A4
P 4350 5000
F 0 "R9" H 4409 5046 50 0000 L CNN
F 1 "220" H 4409 4955 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 4350 5000 50 0001 C CNN
F 3 "~" H 4350 5000 50 0001 C CNN
1 4350 5000
1 0 0 -1
P 10700 7050
F 0 "R9" H 10759 7096 50 0000 L CNN
F 1 "220" H 10759 7005 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 10700 7050 50 0001 C CNN
F 3 "~" H 10700 7050 50 0001 C CNN
1 10700 7050
0 1 1 0
$EndComp
$Comp
L Device:LED D4
U 1 1 61B7C071
P 4350 5300
F 0 "D4" V 4389 5182 50 0000 R CNN
F 1 "LED_FPGA" V 4298 5182 50 0000 R CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 4350 5300 50 0001 C CNN
F 3 "~" H 4350 5300 50 0001 C CNN
1 4350 5300
0 -1 -1 0
P 10400 7050
F 0 "D4" V 10439 6932 50 0000 R CNN
F 1 "LED_FPGA" V 10348 6932 50 0000 R CNN
F 2 "LED_SMD:LED_0603_1608Metric" H 10400 7050 50 0001 C CNN
F 3 "~" H 10400 7050 50 0001 C CNN
1 10400 7050
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR011
U 1 1 61B96C01
P 4350 4750
F 0 "#PWR011" H 4350 4600 50 0001 C CNN
F 1 "+3V3" H 4365 4923 50 0000 C CNN
F 2 "" H 4350 4750 50 0001 C CNN
F 3 "" H 4350 4750 50 0001 C CNN
1 4350 4750
1 0 0 -1
P 10950 7050
F 0 "#PWR011" H 10950 6900 50 0001 C CNN
F 1 "+3V3" H 10965 7223 50 0000 C CNN
F 2 "" H 10950 7050 50 0001 C CNN
F 3 "" H 10950 7050 50 0001 C CNN
1 10950 7050
0 1 1 0
$EndComp
$Comp
L power:GND #PWR012
U 1 1 61C1A434
P 4350 6050
F 0 "#PWR012" H 4350 5800 50 0001 C CNN
F 1 "GND" H 4355 5877 50 0000 C CNN
F 2 "" H 4350 6050 50 0001 C CNN
F 3 "" H 4350 6050 50 0001 C CNN
1 4350 6050
1 0 0 -1
P 9650 7050
F 0 "#PWR012" H 9650 6800 50 0001 C CNN
F 1 "GND" H 9655 6877 50 0000 C CNN
F 2 "" H 9650 7050 50 0001 C CNN
F 3 "" H 9650 7050 50 0001 C CNN
1 9650 7050
0 1 1 0
$EndComp
Wire Wire Line
4350 4900 4350 4850
10800 7050 10850 7050
Wire Wire Line
4350 5100 4350 5150
10600 7050 10550 7050
Wire Wire Line
4350 5450 4350 5500
10250 7050 10200 7050
Wire Wire Line
4350 5900 4350 6000
9800 7050 9700 7050
Wire Wire Line
4350 6000 4350 6050
Connection ~ 4350 6000
9700 7050 9650 7050
Connection ~ 9700 7050
Wire Wire Line
3900 6000 4350 6000
9700 6600 9700 7050
Wire Wire Line
2200 7500 2200 7550
$Comp
L Switch:SW_Push SW?
U 1 1 6100CA18
P 3900 5400
P 10300 6600
AR Path="/60C2FDBB/6100CA18" Ref="SW?" Part="1"
AR Path="/60C0E996/6100CA18" Ref="SW1" Part="1"
F 0 "SW1" H 3900 5685 50 0000 C CNN
F 1 "SW_FPGA" H 3900 5594 50 0000 C CNN
F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 3900 5600 50 0001 C CNN
F 3 "~" H 3900 5600 50 0001 C CNN
1 3900 5400
0 -1 -1 0
F 0 "SW1" H 10300 6885 50 0000 C CNN
F 1 "SW_FPGA" H 10300 6794 50 0000 C CNN
F 2 "Button_Switch_SMD:SW_SPST_SKQG_WithoutStem" H 10300 6800 50 0001 C CNN
F 3 "~" H 10300 6800 50 0001 C CNN
1 10300 6600
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R8
U 1 1 61AE7ED5
P 4250 5000
F 0 "R8" H 4309 5046 50 0000 L CNN
F 1 "10k" H 4309 4955 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 4250 5000 50 0001 C CNN
F 3 "~" H 4250 5000 50 0001 C CNN
1 4250 5000
-1 0 0 1
P 10700 6950
F 0 "R8" H 10759 6996 50 0000 L CNN
F 1 "10k" H 10759 6905 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 10700 6950 50 0001 C CNN
F 3 "~" H 10700 6950 50 0001 C CNN
1 10700 6950
0 -1 -1 0
$EndComp
Wire Wire Line
3900 4700 3900 5150
11000 6600 10550 6600
Wire Wire Line
4250 4900 4250 4850
10800 6950 10850 6950
Wire Wire Line
4250 4850 4350 4850
10850 6950 10850 7050
Wire Wire Line
4350 4850 4350 4750
Connection ~ 4350 4850
10850 7050 10950 7050
Connection ~ 10850 7050
Wire Wire Line
4250 5100 4250 5150
10600 6950 10550 6950
Wire Wire Line
4250 5150 3900 5150
Connection ~ 3900 5150
10550 6950 10550 6600
Connection ~ 10550 6600
Wire Wire Line
3900 5150 3900 5200
10550 6600 10500 6600
Wire Wire Line
3900 5600 3900 6000
10100 6600 9700 6600
$Comp
L TestAutomation:ICE40HX8K-CT256 U3
U 5 1 6256A27C
@ -2508,119 +2508,12 @@ Wire Wire Line
8150 3900 8300 3900
Wire Wire Line
8150 4000 8300 4000
Text Label 12050 1050 0 50 ~ 0
LVDS0_0_P
Text Label 12050 1150 0 50 ~ 0
LVDS0_0_N
Text Label 12050 1250 0 50 ~ 0
LVDS0_1_P
Text Label 12050 1350 0 50 ~ 0
LVDS0_1_N
Text Label 12050 1450 0 50 ~ 0
LVDS0_2_P
Text Label 12050 1550 0 50 ~ 0
LVDS0_2_N
Text Label 12050 1650 0 50 ~ 0
LVDS0_3_P
Text Label 12050 1750 0 50 ~ 0
LVDS0_3_N
Text Label 12050 1850 0 50 ~ 0
LVDS0_4_P
Text Label 12050 1950 0 50 ~ 0
LVDS0_4_N
Text Label 12050 2050 0 50 ~ 0
LVDS0_5_P
Text Label 12050 2150 0 50 ~ 0
LVDS0_5_N
Text Label 12050 2250 0 50 ~ 0
LVDS0_6_P
Text Label 12050 2350 0 50 ~ 0
LVDS0_6_N
Text Label 12050 2450 0 50 ~ 0
LVDS0_7_P
Text Label 12050 2550 0 50 ~ 0
LVDS0_7_N
Text Label 12050 2650 0 50 ~ 0
LVDS1_0_P
Text Label 12050 2750 0 50 ~ 0
LVDS1_0_N
Text Label 12050 2850 0 50 ~ 0
LVDS1_1_P
Text Label 12050 2950 0 50 ~ 0
LVDS1_1_N
Text Label 12050 3050 0 50 ~ 0
LVDS1_2_P
Text Label 12050 3150 0 50 ~ 0
LVDS1_2_N
Text Label 12050 3250 0 50 ~ 0
LVDS1_3_P
Text Label 12050 3350 0 50 ~ 0
LVDS1_3_N
Text Label 12050 3450 0 50 ~ 0
LVDS1_4_P
Text Label 12050 3550 0 50 ~ 0
LVDS1_4_N
Text Label 12050 3650 0 50 ~ 0
LVDS1_5_P
Text Label 12050 3750 0 50 ~ 0
LVDS1_5_N
Text Label 12050 3850 0 50 ~ 0
LVDS1_6_P
Text Label 12050 3950 0 50 ~ 0
LVDS1_6_N
Text Label 12050 4050 0 50 ~ 0
LVDS1_7_P
Text Label 12050 4150 0 50 ~ 0
LVDS1_7_N
Text Label 12050 4250 0 50 ~ 0
LVDS2_0_P
Text Label 12050 4350 0 50 ~ 0
LVDS2_0_N
Text Label 12050 4450 0 50 ~ 0
LVDS2_1_P
Text Label 12050 4550 0 50 ~ 0
LVDS2_1_N
Text Label 12050 4650 0 50 ~ 0
LVDS2_2_P
Text Label 12050 4750 0 50 ~ 0
LVDS2_2_N
Text Label 12050 4850 0 50 ~ 0
LVDS2_3_P
Text Label 12050 4950 0 50 ~ 0
LVDS2_3_N
Text Label 12050 5050 0 50 ~ 0
LVDS2_4_P
Text Label 12050 5150 0 50 ~ 0
LVDS2_4_N
Text Label 12050 5250 0 50 ~ 0
LVDS2_5_P
Text Label 12050 5350 0 50 ~ 0
LVDS2_5_N
Text Label 12050 5450 0 50 ~ 0
LVDS2_6_P
Text Label 12050 5550 0 50 ~ 0
LVDS2_6_N
Text Label 12050 5650 0 50 ~ 0
LVDS2_7_P
Text Label 12050 5750 0 50 ~ 0
LVDS2_7_N
Text Label 12050 5850 0 50 ~ 0
LVDS3_1_P
Text Label 12050 5950 0 50 ~ 0
LVDS3_1_N
Text Label 12050 6050 0 50 ~ 0
LVDS3_2_P
Text Label 12050 6150 0 50 ~ 0
LVDS3_2_N
NoConn ~ 3750 4800
NoConn ~ 3750 4900
NoConn ~ 3750 5000
NoConn ~ 3750 5100
NoConn ~ 3750 5200
NoConn ~ 3750 5300
NoConn ~ 3750 5400
NoConn ~ 3750 5500
NoConn ~ 3750 5600
NoConn ~ 3750 5700
NoConn ~ 3750 5800
NoConn ~ 3750 5900
@ -2746,9 +2639,9 @@ Wire Wire Line
5850 4400 5750 4400
Wire Wire Line
5750 5000 5850 5000
Text Label 3900 4700 1 50 ~ 0
Text Label 11000 6600 0 50 ~ 0
FPGA_KEY
Text Label 4050 4600 1 50 ~ 0
Text Label 11100 6750 0 50 ~ 0
FPGA_LED
Text HLabel 1850 2600 2 50 Input ~ 0
FPGA_FSMC_A2
@ -2766,4 +2659,48 @@ Wire Wire Line
1850 2000 1800 2000
Text HLabel 1850 2000 2 50 Input ~ 0
FPGA_FSMC_A7
NoConn ~ 1800 1100
NoConn ~ 1800 1400
NoConn ~ 1800 1900
NoConn ~ 1800 2100
NoConn ~ 1800 2800
NoConn ~ 1800 3000
NoConn ~ 1800 3100
NoConn ~ 1800 3300
NoConn ~ 1800 3500
NoConn ~ 1800 3700
NoConn ~ 1800 4300
NoConn ~ 1800 4400
NoConn ~ 1800 4600
NoConn ~ 1800 4900
NoConn ~ 1800 5200
NoConn ~ 1800 5400
NoConn ~ 1800 5500
NoConn ~ 1800 5700
NoConn ~ 1800 5800
NoConn ~ 1800 5900
NoConn ~ 3750 4600
NoConn ~ 3750 4500
NoConn ~ 3750 4400
NoConn ~ 3750 4200
NoConn ~ 3750 4100
NoConn ~ 3750 4000
NoConn ~ 3750 3800
NoConn ~ 3750 3600
NoConn ~ 3750 3500
NoConn ~ 3750 3300
NoConn ~ 3750 3200
NoConn ~ 3750 3100
NoConn ~ 3750 2700
NoConn ~ 3750 2600
NoConn ~ 3750 2400
NoConn ~ 3750 2200
NoConn ~ 3750 2000
NoConn ~ 3750 1900
NoConn ~ 3750 1600
NoConn ~ 3750 1500
NoConn ~ 3750 1400
NoConn ~ 3750 1100
NoConn ~ 3750 1000
NoConn ~ 3750 900
$EndSCHEMATC

File diff suppressed because it is too large Load Diff