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PCB: finish routing

master
Jack-Zheng 2021-06-28 15:34:20 +08:00
parent 53accc8761
commit 185f9eacda
2 changed files with 8274 additions and 582 deletions
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34
MCU.sch
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@ -539,10 +539,10 @@ Wire Wire Line
2600 5450 3000 5450
Wire Wire Line
5000 4150 5350 4150
Text HLabel 5400 2950 2 50 Input ~ 0
Text HLabel 5400 6450 2 50 Input ~ 0
CPU_ENC_CS
Wire Wire Line
5400 2950 5000 2950
5400 6450 5000 6450
$Comp
L Device:L L?
U 1 1 6115CE70
@ -1093,42 +1093,41 @@ Wire Wire Line
Wire Wire Line
7100 5400 7100 5250
Connection ~ 7100 5250
Text HLabel 5400 2850 2 50 Input ~ 0
Text HLabel 5400 6550 2 50 Input ~ 0
CPU_ENC_INT
Text HLabel 5400 2550 2 50 Input ~ 0
Text HLabel 5400 4050 2 50 Input ~ 0
CPU_12V_SW
Text HLabel 5400 3650 2 50 Input ~ 0
Text HLabel 5400 6650 2 50 Input ~ 0
CPU_POE_AT_EVENT
Text HLabel 5400 3550 2 50 Input ~ 0
CPU_POE_SRC_STATUS
Wire Wire Line
5400 6450 5000 6450
5400 2950 5000 2950
Wire Wire Line
5000 6550 5400 6550
5000 6350 5400 6350
Wire Wire Line
5400 6650 5000 6650
5400 2850 5000 2850
Wire Wire Line
5400 3550 5000 3550
Wire Wire Line
5400 2550 5000 2550
5400 4050 5000 4050
Wire Wire Line
5000 2850 5400 2850
5000 6550 5400 6550
Wire Wire Line
5000 3650 5400 3650
Text HLabel 5400 6350 2 50 Input ~ 0
5000 6650 5400 6650
Text HLabel 5400 2550 2 50 Input ~ 0
CPU_FPGA_CSBSEL0
Text HLabel 5400 6450 2 50 Input ~ 0
Text HLabel 5400 2950 2 50 Input ~ 0
CPU_FPGA_CSBSEL1
Text HLabel 5400 6550 2 50 Input ~ 0
Text HLabel 5400 6350 2 50 Input ~ 0
CPU_FPGA_CDONE
Text HLabel 5400 6650 2 50 Input ~ 0
Text HLabel 5400 2850 2 50 Input ~ 0
CPU_FPGA_CRESET
Wire Wire Line
5000 6350 5400 6350
5000 2550 5400 2550
NoConn ~ 5000 5350
NoConn ~ 5000 5450
NoConn ~ 3000 5350
NoConn ~ 5000 4050
$Comp
L TestAutomation:FTSH-105-XX-X-DV J7
U 1 1 6258FCEE
@ -1202,4 +1201,5 @@ NoConn ~ 8700 2250
NoConn ~ 8700 2350
NoConn ~ 7700 2350
NoConn ~ 7700 2250
NoConn ~ 5000 3650
$EndSCHEMATC

8822
TestAutomation.kicad_pcb
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