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7a0fa5ce04
add TPS2590 to make 3v3_MP output controllable and limit current; update 12v output current limit to 1A
mikelam
2022-02-13 17:34:01 +0800
7060490ce2
v1.1 release
mikelam
2022-02-12 16:29:23 +0800
b3427d68c6
use 2x17 connector for FPGA_IO and 2x12 connector for Analog; use FPGA GBIN pins for FSMC and HSADC clocks
mikelam
2022-02-07 23:28:10 +0800
112e812159
see update log for details
Jack-Zheng
2021-08-31 17:36:44 +0800
f0f70afd86
schematic: fix bugs; all: add update log
Jack-Zheng
2021-07-23 17:01:52 +0800
d02478566d
PCB: replace ice40 package with default library BGA256
Jack-Zheng
2021-07-15 14:55:30 +0800
6547fb7beb
fix logo resolution issue, fix AG5300 module pin bug, update crystal package, add SMT positioning hole; FabricationOutput: add SMT position and BOM file; v1.0 production release
Jack-Zheng
2021-07-23 17:04:18 +0800
22cd0f4c9d
PCB: fix logo resolution issue, fix AG5300 module pin bug, update crystal package, add SMT positioning hole; FabricationOutput: add SMT position and BOM file
Jack-Zheng
2021-07-14 14:33:32 +0800
c2195f89ef
PCB: finalized output
Jack-Zheng
2021-07-12 14:41:07 +0800
74e9c8aab6
all: export fabrication output
Jack-Zheng
2021-07-12 12:02:45 +0800
9aeb94f2c9
PCB: add screw hole keep out
Jack-Zheng
2021-07-12 11:29:03 +0800
e0ef7d6e7f
FPGA: fix IIC ESD protection bug
Jack-Zheng
2021-07-12 10:03:25 +0800
09ebd078c2
CurrentSenser: connect reference voltage to MCU ADC
Jack-Zheng
2021-07-10 13:19:05 +0800
66d7d68a55
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
Jack-Zheng
2021-07-09 20:18:06 +0800
3dd53b1fe4
PCB: refill polygon
Jack-Zheng
2021-07-09 16:19:37 +0800
3a06817165
CurrentSense: connect FAULT signal to MCU
Jack-Zheng
2021-07-09 16:07:40 +0800
191eacdf8c
HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout; LVDS&IO: fix name issue
Jack-Zheng
2021-07-09 14:35:41 +0800
f9574a2098
HSADC: reselect new op amp
Jack-Zheng
2021-07-07 17:26:54 +0800
3228e16c8f
MCU, FPGA, Ethernet, PCB: fix decoupling capacitors
Jack-Zheng
2021-07-07 16:14:10 +0800
90053d4887
PowerSupply: fix TVS protection bug; PCB: finish routing
Jack-Zheng
2021-07-06 15:41:17 +0800
eceba52792
PCB & FPGA & MCU: fix LVDS impedance issues
Jack-Zheng
2021-07-06 10:28:18 +0800
1b592eed37
FPGA & MCU & PCB: add decoupling capactors
Jack-Zheng
2021-07-02 11:04:53 +0800
f796eedc08
PCB: fix grand dead zones
Jack-Zheng
2021-06-30 15:24:25 +0800
4853b02184
PCB: replace 0201 resistors to 0402 as JLC cannot do SMT for 0201
Jack-Zheng
2021-06-30 14:59:13 +0800
93ba0cbe9d
HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout
Jack-Zheng
2021-06-30 14:51:30 +0800
17127387c9
PCB: optimize buck converter and shunt resistor layout
Jack-Zheng
2021-06-30 11:36:53 +0800
26d727f8c5
PCB: replace LVDS resistors with 0201 package, optimize LVDS pairs layout
Jack-Zheng
2021-06-29 16:49:26 +0800
8ffd698079
PCB: optimize HSADC layout
Jack-Zheng
2021-06-29 10:38:12 +0800
6584f44f2a
PCB: fix GND polygon dead zones; all: export BOM
Jack-Zheng
2021-06-29 10:26:02 +0800
10818a4771
PCB: fix small LVDS connection issue
Jack-Zheng
2021-06-28 15:49:33 +0800
a16bee581b
PCB: fix small LVDS connection issue
Jack-Zheng
2021-06-28 15:45:06 +0800
185f9eacda
PCB: finish routing
Jack-Zheng
2021-06-28 15:34:20 +0800
53accc8761
PCB: finish IO and analog connectors
Jack-Zheng
2021-06-28 10:40:21 +0800
4b15f466a0
PCB: finish SWD, IIC
Jack-Zheng
2021-06-25 18:15:56 +0800
0e1120d266
FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing
Jack-Zheng
2021-06-25 16:57:46 +0800
2a31c8b3f3
PCB: finish LVDS routing
Jack-Zheng
2021-06-24 15:18:57 +0800
37941bfc2c
PCB: finalize component positions and define board shape
Jack-Zheng
2021-06-22 17:14:32 +0800
6535ff5423
LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
Jack-Zheng
2021-06-22 16:34:02 +0800
1df738664f
all: update gitignore; remove redundant files
Jack-Zheng
2021-06-22 09:44:50 +0800
b740887ac2
HighSpeedADC: fix chip rotation bug, remove SMA connector; all: fix BJT base resistors; Power: remove DC jack; LVDS&IO: replace IDC header with dupont
Jack-Zheng
2021-06-21 17:06:20 +0800
982fefd6b5
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
Jack-Zheng
2021-06-21 16:05:17 +0800
327abdeb24
CurrentSensor: fix bugs and replace opamp with current senser
Jack-Zheng
2021-06-21 15:10:25 +0800
9bcc9a229b
TestAutomation: replace messy wires with bus
Jack-Zheng
2021-06-21 12:10:31 +0800
45940c1ac8
all: finish routing
Jack-Zheng
2021-06-18 16:13:42 +0800
9c10edde19
CurrentSensor: add mid point voltage reference; FPGA: fix pinout
Jack-Zheng
2021-06-18 14:24:15 +0800
0cebd6ed2b
LVDS: add LVDS ports; all: add LEDs
Jack-Zheng
2021-06-18 11:30:16 +0800
74f4fc201a
FPGA: add GPIO and ADC parallel port
Jack-Zheng
2021-06-18 10:27:05 +0800
9a62476f9e
MCU: finish connectors
Jack-Zheng
2021-06-17 17:33:12 +0800
4123caa996
all: add gitignore; remove redundant files from repo; optimize file name style
Jack-Zheng
2021-06-17 15:46:02 +0800
6cee2d0419
Current_Senser: add current sampling; all: optimize +3.3VA
Jack-Zheng
2021-06-17 15:30:51 +0800
9f7ffb7754
docs: remove unused Chinese docs
Jack-Zheng
2021-06-17 11:12:40 +0800
dfe4255a21
MCU: finish FSMC, PWM
Jack-Zheng
2021-06-17 10:52:33 +0800
fc8c667020
Power: fix hierarchical and global label
Jack-Zheng
2021-06-16 17:20:32 +0800
5b4801ff74
FPGA: finish EEM, I2C, CFG, SPI FLASH
Jack-Zheng
2021-06-16 17:13:34 +0800
fc2cb47610
all: map symbol and footpins
Jack-Zheng
2021-06-16 15:23:18 +0800
24471104a5
Analog_LVDS: finish ADC
Jack-Zheng
2021-06-16 11:36:49 +0800
66188cd3ad
Ethernet: finish ethernet controller and PoE input
Jack-Zheng
2021-06-15 16:49:17 +0800
e28d01d115
PowerSupply: finish power supply part: 12V --(DCDC)--> 6.5V --(LDO)--> 5V+3.3V+2.5V+1.2V
Jack-Zheng
2021-06-11 16:57:49 +0800
83bc618f77
PowerSupply: finish PoE and 12V input schematic
Jack-Zheng
2021-06-11 10:27:09 +0800
232af06c28
components confirmed; datasheet collected; framework finished
Jack-Zheng
2021-06-10 15:16:21 +0800
da19dad9cd
init project
Jack-Zheng
2021-06-07 14:43:54 +0800
mikelam
Jack-Zheng