sinara-hw/Syrostan
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KiCad Schematic 100%
2a31c8b3f3
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Jack-Zheng 2a31c8b3f3 PCB: finish LVDS routing
2021-06-24 15:43:31 +08:00
STM32CubeMx TestAutomation: replace messy wires with bus 2021-06-21 12:10:31 +08:00
TestAutomation.pretty LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout 2021-06-22 16:34:02 +08:00
.gitignore all: update gitignore; remove redundant files 2021-06-22 09:44:50 +08:00
CurrentSenser.sch PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
Ethernet.sch PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
fp-lib-table all: update gitigore to fix symbol and footpin bugs; replace messy libs into one 2021-06-21 16:05:17 +08:00
FPGA.sch PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
HighSpeedADC.sch LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout 2021-06-22 16:34:02 +08:00
LVDS&IO.sch PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
MCU.sch PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
Power.sch PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
sym-lib-table all: update gitigore to fix symbol and footpin bugs; replace messy libs into one 2021-06-21 16:05:17 +08:00
TestAutomation.bck all: update gitigore to fix symbol and footpin bugs; replace messy libs into one 2021-06-21 16:05:17 +08:00
TestAutomation.dcm all: update gitigore to fix symbol and footpin bugs; replace messy libs into one 2021-06-21 16:05:17 +08:00
TestAutomation.kicad_pcb PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
TestAutomation.lib all: update gitigore to fix symbol and footpin bugs; replace messy libs into one 2021-06-21 16:05:17 +08:00
TestAutomation.net PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
TestAutomation.pro PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00
TestAutomation.sch PCB: finish LVDS routing 2021-06-24 15:43:31 +08:00