MCU: finish FSMC, PWM
parent
fc8c667020
commit
dfe4255a21
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@ -3,7 +3,7 @@ EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 5 6
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Sheet 4 6
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Title ""
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Date ""
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Rev ""
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@ -3,7 +3,7 @@ EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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||||
encoding utf-8
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||||
Sheet 5 6
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||||
Sheet 4 6
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Title ""
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Date ""
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Rev ""
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8
FPGA.sch
8
FPGA.sch
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@ -3,7 +3,7 @@ EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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||||
encoding utf-8
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||||
Sheet 2 6
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Sheet 3 6
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Title ""
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Date ""
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Rev ""
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@ -2159,7 +2159,7 @@ U 1 1 62CE70DD
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P 8700 7000
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F 0 "R113" V 8493 7000 50 0000 C CNN
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||||
F 1 "10k" V 8584 7000 50 0000 C CNN
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||||
F 2 "" V 8630 7000 50 0001 C CNN
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||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 8630 7000 50 0001 C CNN
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||||
F 3 "~" H 8700 7000 50 0001 C CNN
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1 8700 7000
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0 1 1 0
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@ -2170,7 +2170,7 @@ U 1 1 62CBFB4D
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P 8700 6900
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F 0 "R112" V 8493 6900 50 0000 C CNN
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||||
F 1 "10k" V 8584 6900 50 0000 C CNN
|
||||
F 2 "" V 8630 6900 50 0001 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 8630 6900 50 0001 C CNN
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F 3 "~" H 8700 6900 50 0001 C CNN
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1 8700 6900
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0 1 1 0
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@ -2181,7 +2181,7 @@ U 1 1 62C9E4F5
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|||
P 8700 6800
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||||
F 0 "R111" V 8493 6800 50 0000 C CNN
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||||
F 1 "10k" V 8584 6800 50 0000 C CNN
|
||||
F 2 "" V 8630 6800 50 0001 C CNN
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||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 8630 6800 50 0001 C CNN
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F 3 "~" H 8700 6800 50 0001 C CNN
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1 8700 6800
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0 1 1 0
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@ -3,7 +3,7 @@ EELAYER 30 0
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EELAYER END
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||||
$Descr A4 11693 8268
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||||
encoding utf-8
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||||
Sheet 2 6
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Sheet 3 6
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Title ""
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Date ""
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Rev ""
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||||
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@ -2159,7 +2159,7 @@ U 1 1 62CE70DD
|
|||
P 8700 7000
|
||||
F 0 "R113" V 8493 7000 50 0000 C CNN
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||||
F 1 "10k" V 8584 7000 50 0000 C CNN
|
||||
F 2 "" V 8630 7000 50 0001 C CNN
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||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 8630 7000 50 0001 C CNN
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||||
F 3 "~" H 8700 7000 50 0001 C CNN
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1 8700 7000
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0 1 1 0
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||||
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@ -2170,7 +2170,7 @@ U 1 1 62CBFB4D
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P 8700 6900
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||||
F 0 "R112" V 8493 6900 50 0000 C CNN
|
||||
F 1 "10k" V 8584 6900 50 0000 C CNN
|
||||
F 2 "" V 8630 6900 50 0001 C CNN
|
||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 8630 6900 50 0001 C CNN
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F 3 "~" H 8700 6900 50 0001 C CNN
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||||
1 8700 6900
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||||
0 1 1 0
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||||
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@ -2181,7 +2181,7 @@ U 1 1 62C9E4F5
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|||
P 8700 6800
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||||
F 0 "R111" V 8493 6800 50 0000 C CNN
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||||
F 1 "10k" V 8584 6800 50 0000 C CNN
|
||||
F 2 "" V 8630 6800 50 0001 C CNN
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||||
F 2 "Resistor_SMD:R_0603_1608Metric" V 8630 6800 50 0001 C CNN
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F 3 "~" H 8700 6800 50 0001 C CNN
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1 8700 6800
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0 1 1 0
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168
MCU.sch
168
MCU.sch
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@ -3,7 +3,7 @@ EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 4 6
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Sheet 6 6
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Title ""
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Date ""
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Rev ""
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@ -349,24 +349,6 @@ Wire Wire Line
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5000 5550 5400 5550
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Wire Wire Line
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5000 5650 5400 5650
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Wire Wire Line
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3000 4150 2450 4150
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Wire Wire Line
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3000 4250 2450 4250
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Wire Wire Line
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||||
3000 4350 2450 4350
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Wire Wire Line
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3000 4450 2450 4450
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||||
Wire Wire Line
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||||
3000 4550 2450 4550
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||||
Wire Wire Line
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3000 4650 2450 4650
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||||
Wire Wire Line
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||||
3000 4750 2450 4750
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Wire Wire Line
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3000 4850 2450 4850
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||||
Wire Wire Line
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||||
3000 4950 2450 4950
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Text HLabel 5350 4450 2 50 Input ~ 0
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CPU_IIC2_SCL
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Text HLabel 5350 4550 2 50 Input ~ 0
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||||
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@ -439,4 +421,152 @@ Text HLabel 5400 3250 2 50 Input ~ 0
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CPU_SPI1_CS
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Wire Wire Line
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5000 3250 5400 3250
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Text HLabel 2600 6550 0 50 Input ~ 0
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CPU_FSMC_DA0
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Text HLabel 2600 6650 0 50 Input ~ 0
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CPU_FSMC_DA1
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Wire Wire Line
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2600 6550 3000 6550
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Wire Wire Line
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2600 6650 3000 6650
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Text HLabel 2600 5150 0 50 Input ~ 0
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CPU_FSMC_DA2
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Text HLabel 2600 5250 0 50 Input ~ 0
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CPU_FSMC_DA3
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Text HLabel 2600 4150 0 50 Input ~ 0
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CPU_FSMC_DA4
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Text HLabel 2600 4250 0 50 Input ~ 0
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CPU_FSMC_DA5
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Text HLabel 2600 4350 0 50 Input ~ 0
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CPU_FSMC_DA6
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Text HLabel 2600 4450 0 50 Input ~ 0
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CPU_FSMC_DA7
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Text HLabel 2600 4550 0 50 Input ~ 0
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CPU_FSMC_DA8
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Text HLabel 2600 4650 0 50 Input ~ 0
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CPU_FSMC_DA9
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Text HLabel 2600 4750 0 50 Input ~ 0
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CPU_FSMC_DA10
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Text HLabel 2600 4850 0 50 Input ~ 0
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CPU_FSMC_DA11
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Text HLabel 2600 4950 0 50 Input ~ 0
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CPU_FSMC_DA12
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Wire Wire Line
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2600 4150 3000 4150
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Wire Wire Line
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2600 4250 3000 4250
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Wire Wire Line
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2600 4350 3000 4350
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Wire Wire Line
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2600 4450 3000 4450
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||||
Wire Wire Line
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2600 4550 3000 4550
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Wire Wire Line
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2600 4650 3000 4650
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Wire Wire Line
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3000 4750 2600 4750
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Wire Wire Line
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2600 4850 3000 4850
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Wire Wire Line
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2600 4950 3000 4950
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Wire Wire Line
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2600 5150 3000 5150
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Wire Wire Line
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2600 5250 3000 5250
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Text HLabel 2600 5950 0 50 Input ~ 0
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CPU_FSMC_D13
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Text HLabel 2600 6050 0 50 Input ~ 0
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CPU_FSMC_D14
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Text HLabel 2600 6150 0 50 Input ~ 0
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CPU_FSMC_D15
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||||
Wire Wire Line
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2600 5950 3000 5950
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Wire Wire Line
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2600 6050 3000 6050
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Wire Wire Line
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2600 6150 3000 6150
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Text HLabel 2600 6250 0 50 Input ~ 0
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CPU_FSMC_A16
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Text HLabel 2600 6350 0 50 Input ~ 0
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CPU_FSMC_A17
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Text HLabel 2600 6450 0 50 Input ~ 0
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CPU_FSMC_A18
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||||
Wire Wire Line
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2600 6250 3000 6250
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Wire Wire Line
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2600 6350 3000 6350
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Wire Wire Line
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2600 6450 3000 6450
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Text HLabel 2600 3750 0 50 Input ~ 0
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CPU_FSMC_A19
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Text HLabel 2600 3850 0 50 Input ~ 0
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CPU_FSMC_A20
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Text HLabel 2600 3950 0 50 Input ~ 0
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CPU_FSMC_A21
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Text HLabel 2600 4050 0 50 Input ~ 0
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CPU_FSMC_A22
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Text HLabel 2600 3650 0 50 Input ~ 0
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CPU_FSMC_A23
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Wire Wire Line
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3000 3650 2600 3650
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Wire Wire Line
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2600 3750 3000 3750
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Wire Wire Line
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3000 3850 2600 3850
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Wire Wire Line
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2600 3950 3000 3950
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Wire Wire Line
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3000 4050 2600 4050
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Text HLabel 2600 5650 0 50 Input ~ 0
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CPU_FSMC_NWE
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Text HLabel 2600 5550 0 50 Input ~ 0
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CPU_FSMC_NOE
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Wire Wire Line
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2600 5550 3000 5550
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Wire Wire Line
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2600 5650 3000 5650
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Text HLabel 2600 5850 0 50 Input ~ 0
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CPU_FSMC_NE1
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Wire Wire Line
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2600 5850 3000 5850
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Text HLabel 5400 5750 2 50 Input ~ 0
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CPU_PWM_CH1
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Text HLabel 5400 5850 2 50 Input ~ 0
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CPU_PWM_CH2
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Text HLabel 5400 5950 2 50 Input ~ 0
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CPU_PWM_CH3
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Text HLabel 5400 6050 2 50 Input ~ 0
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CPU_PWM_CH4
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||||
Wire Wire Line
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5400 5750 5000 5750
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Wire Wire Line
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5000 5850 5400 5850
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Wire Wire Line
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5400 5950 5000 5950
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Wire Wire Line
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5000 6050 5400 6050
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Text HLabel 2600 3450 0 50 Input ~ 0
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CPU_FSMC_NBL0
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Text HLabel 2600 3550 0 50 Input ~ 0
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||||
CPU_FSMC_NBL1
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||||
Wire Wire Line
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||||
2600 3450 3000 3450
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Wire Wire Line
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3000 3550 2600 3550
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||||
Text HLabel 5350 4150 2 50 Input ~ 0
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CPU_FSMC_NL
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||||
Text HLabel 2600 5450 0 50 Input ~ 0
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||||
CPU_FSMC_CLK
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||||
Text HLabel 2600 5750 0 50 Input ~ 0
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||||
CPU_FSMC_NWAIT
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||||
Wire Wire Line
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||||
2600 5750 3000 5750
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||||
Wire Wire Line
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||||
2600 5450 3000 5450
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||||
Wire Wire Line
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||||
5000 4150 5350 4150
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||||
Text HLabel 5400 2950 2 50 Input ~ 0
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||||
CPU_ENC_CS
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||||
Wire Wire Line
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||||
5400 2950 5000 2950
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||||
$EndSCHEMATC
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||||
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|||
168
MCU.sch-bak
168
MCU.sch-bak
|
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@ -3,7 +3,7 @@ EELAYER 30 0
|
|||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 4 6
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||||
Sheet 6 6
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||||
Title ""
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||||
Date ""
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||||
Rev ""
|
||||
|
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@ -349,24 +349,6 @@ Wire Wire Line
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|||
5000 5550 5400 5550
|
||||
Wire Wire Line
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||||
5000 5650 5400 5650
|
||||
Wire Wire Line
|
||||
3000 4150 2450 4150
|
||||
Wire Wire Line
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||||
3000 4250 2450 4250
|
||||
Wire Wire Line
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||||
3000 4350 2450 4350
|
||||
Wire Wire Line
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||||
3000 4450 2450 4450
|
||||
Wire Wire Line
|
||||
3000 4550 2450 4550
|
||||
Wire Wire Line
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||||
3000 4650 2450 4650
|
||||
Wire Wire Line
|
||||
3000 4750 2450 4750
|
||||
Wire Wire Line
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||||
3000 4850 2450 4850
|
||||
Wire Wire Line
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||||
3000 4950 2450 4950
|
||||
Text HLabel 5350 4450 2 50 Input ~ 0
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||||
CPU_IIC2_SCL
|
||||
Text HLabel 5350 4550 2 50 Input ~ 0
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||||
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@ -439,4 +421,152 @@ Text HLabel 5400 3250 2 50 Input ~ 0
|
|||
CPU_SPI1_CS
|
||||
Wire Wire Line
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||||
5000 3250 5400 3250
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||||
Text HLabel 2600 6550 0 50 Input ~ 0
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||||
CPU_FSMC_DA0
|
||||
Text HLabel 2600 6650 0 50 Input ~ 0
|
||||
CPU_FSMC_DA1
|
||||
Wire Wire Line
|
||||
2600 6550 3000 6550
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||||
Wire Wire Line
|
||||
2600 6650 3000 6650
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||||
Text HLabel 2600 5150 0 50 Input ~ 0
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||||
CPU_FSMC_DA2
|
||||
Text HLabel 2600 5250 0 50 Input ~ 0
|
||||
CPU_FSMC_DA3
|
||||
Text HLabel 2600 4150 0 50 Input ~ 0
|
||||
CPU_FSMC_DA4
|
||||
Text HLabel 2600 4250 0 50 Input ~ 0
|
||||
CPU_FSMC_DA5
|
||||
Text HLabel 2600 4350 0 50 Input ~ 0
|
||||
CPU_FSMC_DA6
|
||||
Text HLabel 2600 4450 0 50 Input ~ 0
|
||||
CPU_FSMC_DA7
|
||||
Text HLabel 2600 4550 0 50 Input ~ 0
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||||
CPU_FSMC_DA8
|
||||
Text HLabel 2600 4650 0 50 Input ~ 0
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||||
CPU_FSMC_DA9
|
||||
Text HLabel 2600 4750 0 50 Input ~ 0
|
||||
CPU_FSMC_DA10
|
||||
Text HLabel 2600 4850 0 50 Input ~ 0
|
||||
CPU_FSMC_DA11
|
||||
Text HLabel 2600 4950 0 50 Input ~ 0
|
||||
CPU_FSMC_DA12
|
||||
Wire Wire Line
|
||||
2600 4150 3000 4150
|
||||
Wire Wire Line
|
||||
2600 4250 3000 4250
|
||||
Wire Wire Line
|
||||
2600 4350 3000 4350
|
||||
Wire Wire Line
|
||||
2600 4450 3000 4450
|
||||
Wire Wire Line
|
||||
2600 4550 3000 4550
|
||||
Wire Wire Line
|
||||
2600 4650 3000 4650
|
||||
Wire Wire Line
|
||||
3000 4750 2600 4750
|
||||
Wire Wire Line
|
||||
2600 4850 3000 4850
|
||||
Wire Wire Line
|
||||
2600 4950 3000 4950
|
||||
Wire Wire Line
|
||||
2600 5150 3000 5150
|
||||
Wire Wire Line
|
||||
2600 5250 3000 5250
|
||||
Text HLabel 2600 5950 0 50 Input ~ 0
|
||||
CPU_FSMC_D13
|
||||
Text HLabel 2600 6050 0 50 Input ~ 0
|
||||
CPU_FSMC_D14
|
||||
Text HLabel 2600 6150 0 50 Input ~ 0
|
||||
CPU_FSMC_D15
|
||||
Wire Wire Line
|
||||
2600 5950 3000 5950
|
||||
Wire Wire Line
|
||||
2600 6050 3000 6050
|
||||
Wire Wire Line
|
||||
2600 6150 3000 6150
|
||||
Text HLabel 2600 6250 0 50 Input ~ 0
|
||||
CPU_FSMC_A16
|
||||
Text HLabel 2600 6350 0 50 Input ~ 0
|
||||
CPU_FSMC_A17
|
||||
Text HLabel 2600 6450 0 50 Input ~ 0
|
||||
CPU_FSMC_A18
|
||||
Wire Wire Line
|
||||
2600 6250 3000 6250
|
||||
Wire Wire Line
|
||||
2600 6350 3000 6350
|
||||
Wire Wire Line
|
||||
2600 6450 3000 6450
|
||||
Text HLabel 2600 3750 0 50 Input ~ 0
|
||||
CPU_FSMC_A19
|
||||
Text HLabel 2600 3850 0 50 Input ~ 0
|
||||
CPU_FSMC_A20
|
||||
Text HLabel 2600 3950 0 50 Input ~ 0
|
||||
CPU_FSMC_A21
|
||||
Text HLabel 2600 4050 0 50 Input ~ 0
|
||||
CPU_FSMC_A22
|
||||
Text HLabel 2600 3650 0 50 Input ~ 0
|
||||
CPU_FSMC_A23
|
||||
Wire Wire Line
|
||||
3000 3650 2600 3650
|
||||
Wire Wire Line
|
||||
2600 3750 3000 3750
|
||||
Wire Wire Line
|
||||
3000 3850 2600 3850
|
||||
Wire Wire Line
|
||||
2600 3950 3000 3950
|
||||
Wire Wire Line
|
||||
3000 4050 2600 4050
|
||||
Text HLabel 2600 5650 0 50 Input ~ 0
|
||||
CPU_FSMC_NWE
|
||||
Text HLabel 2600 5550 0 50 Input ~ 0
|
||||
CPU_FSMC_NOE
|
||||
Wire Wire Line
|
||||
2600 5550 3000 5550
|
||||
Wire Wire Line
|
||||
2600 5650 3000 5650
|
||||
Text HLabel 2600 5850 0 50 Input ~ 0
|
||||
CPU_FSMC_NE1
|
||||
Wire Wire Line
|
||||
2600 5850 3000 5850
|
||||
Text HLabel 5400 5750 2 50 Input ~ 0
|
||||
CPU_PWM_CH1
|
||||
Text HLabel 5400 5850 2 50 Input ~ 0
|
||||
CPU_PWM_CH2
|
||||
Text HLabel 5400 5950 2 50 Input ~ 0
|
||||
CPU_PWM_CH3
|
||||
Text HLabel 5400 6050 2 50 Input ~ 0
|
||||
CPU_PWM_CH4
|
||||
Wire Wire Line
|
||||
5400 5750 5000 5750
|
||||
Wire Wire Line
|
||||
5000 5850 5400 5850
|
||||
Wire Wire Line
|
||||
5400 5950 5000 5950
|
||||
Wire Wire Line
|
||||
5000 6050 5400 6050
|
||||
Text HLabel 2600 3450 0 50 Input ~ 0
|
||||
CPU_FSMC_NBL0
|
||||
Text HLabel 2600 3550 0 50 Input ~ 0
|
||||
CPU_FSMC_NBL1
|
||||
Wire Wire Line
|
||||
2600 3450 3000 3450
|
||||
Wire Wire Line
|
||||
3000 3550 2600 3550
|
||||
Text HLabel 5350 4150 2 50 Input ~ 0
|
||||
CPU_FSMC_NL
|
||||
Text HLabel 2600 5450 0 50 Input ~ 0
|
||||
CPU_FSMC_CLK
|
||||
Text HLabel 2600 5750 0 50 Input ~ 0
|
||||
CPU_FSMC_NWAIT
|
||||
Wire Wire Line
|
||||
2600 5750 3000 5750
|
||||
Wire Wire Line
|
||||
2600 5450 3000 5450
|
||||
Wire Wire Line
|
||||
5000 4150 5350 4150
|
||||
Text HLabel 5400 2950 2 50 Input ~ 0
|
||||
CPU_ENC_CS
|
||||
Wire Wire Line
|
||||
5400 2950 5000 2950
|
||||
$EndSCHEMATC
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||||
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@ -3,7 +3,7 @@ EELAYER 30 0
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|||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
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||||
Sheet 2 6
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Sheet 5 6
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||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
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|
|
@ -3,7 +3,7 @@ EELAYER 30 0
|
|||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 2 6
|
||||
Sheet 5 6
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
|
|
|
|||
|
|
@ -14,8 +14,10 @@ KeepUserPlacement=false
|
|||
Mcu.Family=STM32F1
|
||||
Mcu.IP0=ADC1
|
||||
Mcu.IP1=DAC
|
||||
Mcu.IP10=UART4
|
||||
Mcu.IP11=USART1
|
||||
Mcu.IP10=TIM3
|
||||
Mcu.IP11=TIM8
|
||||
Mcu.IP12=UART4
|
||||
Mcu.IP13=USART1
|
||||
Mcu.IP2=FSMC
|
||||
Mcu.IP3=I2C1
|
||||
Mcu.IP4=I2C2
|
||||
|
|
@ -24,7 +26,7 @@ Mcu.IP6=RCC
|
|||
Mcu.IP7=SPI1
|
||||
Mcu.IP8=SPI2
|
||||
Mcu.IP9=SYS
|
||||
Mcu.IPNb=12
|
||||
Mcu.IPNb=14
|
||||
Mcu.Name=STM32F103V(C-D-E)Tx
|
||||
Mcu.Package=LQFP100
|
||||
Mcu.Pin0=PE2
|
||||
|
|
@ -62,30 +64,34 @@ Mcu.Pin37=PD13
|
|||
Mcu.Pin38=PD14
|
||||
Mcu.Pin39=PD15
|
||||
Mcu.Pin4=PE6
|
||||
Mcu.Pin40=PA9
|
||||
Mcu.Pin41=PA10
|
||||
Mcu.Pin42=PA13
|
||||
Mcu.Pin43=PA14
|
||||
Mcu.Pin44=PA15
|
||||
Mcu.Pin45=PC10
|
||||
Mcu.Pin46=PC11
|
||||
Mcu.Pin47=PD0
|
||||
Mcu.Pin48=PD1
|
||||
Mcu.Pin49=PD4
|
||||
Mcu.Pin40=PC6
|
||||
Mcu.Pin41=PC7
|
||||
Mcu.Pin42=PC8
|
||||
Mcu.Pin43=PC9
|
||||
Mcu.Pin44=PA9
|
||||
Mcu.Pin45=PA10
|
||||
Mcu.Pin46=PA13
|
||||
Mcu.Pin47=PA14
|
||||
Mcu.Pin48=PA15
|
||||
Mcu.Pin49=PC10
|
||||
Mcu.Pin5=OSC_IN
|
||||
Mcu.Pin50=PD5
|
||||
Mcu.Pin51=PD7
|
||||
Mcu.Pin52=PB3
|
||||
Mcu.Pin53=PB4
|
||||
Mcu.Pin54=PB5
|
||||
Mcu.Pin55=PB8
|
||||
Mcu.Pin56=PB9
|
||||
Mcu.Pin57=VP_SYS_VS_Systick
|
||||
Mcu.Pin50=PC11
|
||||
Mcu.Pin51=PD0
|
||||
Mcu.Pin52=PD1
|
||||
Mcu.Pin53=PD4
|
||||
Mcu.Pin54=PD5
|
||||
Mcu.Pin55=PD7
|
||||
Mcu.Pin56=PB3
|
||||
Mcu.Pin57=PB4
|
||||
Mcu.Pin58=PB5
|
||||
Mcu.Pin59=PB8
|
||||
Mcu.Pin6=OSC_OUT
|
||||
Mcu.Pin60=PB9
|
||||
Mcu.Pin61=VP_SYS_VS_Systick
|
||||
Mcu.Pin7=PA0-WKUP
|
||||
Mcu.Pin8=PA1
|
||||
Mcu.Pin9=PA2
|
||||
Mcu.PinsNb=58
|
||||
Mcu.PinsNb=62
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32F103VCTx
|
||||
|
|
@ -154,6 +160,10 @@ PC4.Locked=true
|
|||
PC4.Signal=ADCx_IN14
|
||||
PC5.Locked=true
|
||||
PC5.Signal=ADCx_IN15
|
||||
PC6.Signal=S_TIM3_CH1
|
||||
PC7.Signal=S_TIM3_CH2
|
||||
PC8.Signal=S_TIM8_CH3
|
||||
PC9.Signal=S_TIM8_CH4
|
||||
PD0.Mode=24b-da1
|
||||
PD0.Signal=FSMC_DA2
|
||||
PD1.Mode=24b-da1
|
||||
|
|
@ -236,7 +246,7 @@ ProjectManager.StackSize=0x400
|
|||
ProjectManager.TargetToolchain=EWARM V8.32
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DAC_Init-DAC-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C2_Init-I2C2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_UART4_Init-UART4-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DAC_Init-DAC-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C2_Init-I2C2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_SPI2_Init-SPI2-false-HAL-true,8-MX_UART4_Init-UART4-false-HAL-true,9-MX_ADC1_Init-ADC1-false-HAL-true,10-MX_FSMC_Init-FSMC-false-HAL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true
|
||||
RCC.APB1Freq_Value=8000000
|
||||
RCC.APB2Freq_Value=8000000
|
||||
RCC.FamilyName=M
|
||||
|
|
@ -264,6 +274,14 @@ SH.COMP_DAC1_group.0=DAC_OUT1,DAC_OUT1
|
|||
SH.COMP_DAC1_group.ConfNb=1
|
||||
SH.COMP_DAC2_group.0=DAC_OUT2,DAC_OUT2
|
||||
SH.COMP_DAC2_group.ConfNb=1
|
||||
SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1
|
||||
SH.S_TIM3_CH1.ConfNb=1
|
||||
SH.S_TIM3_CH2.0=TIM3_CH2,PWM Generation2 CH2
|
||||
SH.S_TIM3_CH2.ConfNb=1
|
||||
SH.S_TIM8_CH3.0=TIM8_CH3,PWM Generation3 CH3
|
||||
SH.S_TIM8_CH3.ConfNb=1
|
||||
SH.S_TIM8_CH4.0=TIM8_CH4,PWM Generation4 CH4
|
||||
SH.S_TIM8_CH4.ConfNb=1
|
||||
SPI1.CalculateBaudRate=4.0 MBits/s
|
||||
SPI1.Direction=SPI_DIRECTION_2LINES
|
||||
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS
|
||||
|
|
@ -276,6 +294,12 @@ SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS
|
|||
SPI2.Mode=SPI_MODE_MASTER
|
||||
SPI2.VirtualNSS=VM_NSSHARD
|
||||
SPI2.VirtualType=VM_MASTER
|
||||
TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
|
||||
TIM3.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
|
||||
TIM3.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2
|
||||
TIM8.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
|
||||
TIM8.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
|
||||
TIM8.IPParameters=Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
|
||||
UART4.IPParameters=VirtualMode
|
||||
UART4.VirtualMode=Asynchronous
|
||||
USART1.IPParameters=VirtualMode
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -123,36 +123,36 @@ F87 "FPGA_CDONE" I L 4650 4200 50
|
|||
F88 "FPGA_CRESET" I L 4650 4300 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 2250 4300 650 1000
|
||||
S 2900 5700 650 1000
|
||||
U 60E4702B
|
||||
F0 "Ethernet" 50
|
||||
F1 "Ethernet.sch" 50
|
||||
F2 "POE_VC+" I L 2250 5200 50
|
||||
F3 "POE_VC-" I L 2250 5100 50
|
||||
F4 "ENC_SPI_SCK" I L 2250 4900 50
|
||||
F5 "ENC_SPI_MOSI" I L 2250 4800 50
|
||||
F6 "ENC_SPI_MISO" I L 2250 4700 50
|
||||
F7 "ENC_INT" I L 2250 4400 50
|
||||
F8 "ENC_SPI_CS" I L 2250 4600 50
|
||||
F2 "POE_VC+" I L 2900 6600 50
|
||||
F3 "POE_VC-" I L 2900 6500 50
|
||||
F4 "ENC_SPI_SCK" I L 2900 6300 50
|
||||
F5 "ENC_SPI_MOSI" I L 2900 6200 50
|
||||
F6 "ENC_SPI_MISO" I L 2900 6100 50
|
||||
F7 "ENC_INT" I L 2900 5800 50
|
||||
F8 "ENC_SPI_CS" I L 2900 6000 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 2250 5750 750 800
|
||||
S 1650 5750 750 800
|
||||
U 60C2FE2A
|
||||
F0 "Power" 50
|
||||
F1 "Power.sch" 50
|
||||
F2 "POE_VC+" I L 2250 5900 50
|
||||
F3 "POE_VC-" I L 2250 6000 50
|
||||
F4 "POE_AT_EVENT" I L 2250 6200 50
|
||||
F5 "POE_SRC_Status" I L 2250 6300 50
|
||||
F6 "POE_CPU_RESET" I L 2250 6400 50
|
||||
F2 "POE_VC+" I L 1650 5900 50
|
||||
F3 "POE_VC-" I L 1650 6000 50
|
||||
F4 "POE_AT_EVENT" I L 1650 6200 50
|
||||
F5 "POE_SRC_Status" I L 1650 6300 50
|
||||
F6 "POE_CPU_RESET" I L 1650 6400 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1750 900 1950 2550
|
||||
S 1750 900 1500 3950
|
||||
U 60C2FDBB
|
||||
F0 "MCU" 50
|
||||
F1 "MCU.sch" 50
|
||||
F2 "CPU_DAC0" I L 1750 1050 50
|
||||
F3 "CPU_DAC1" I L 1750 1150 50
|
||||
F2 "CPU_DAC0" I L 1750 1000 50
|
||||
F3 "CPU_DAC1" I L 1750 1100 50
|
||||
F4 "CPU_ADC1" I L 1750 1400 50
|
||||
F5 "CPU_ADC2" I L 1750 1500 50
|
||||
F6 "CPU_ADC3" I L 1750 1600 50
|
||||
|
|
@ -161,5 +161,60 @@ F8 "CPU_ADC0" I L 1750 1300 50
|
|||
F9 "CPU_ADC5" I L 1750 1800 50
|
||||
F10 "CPU_ADC6" I L 1750 1900 50
|
||||
F11 "CPU_ADC7" I L 1750 2000 50
|
||||
F12 "CPU_IIC2_SCL" I L 1750 2450 50
|
||||
F13 "CPU_IIC2_SDA" I L 1750 2550 50
|
||||
F14 "CPU_SPI2_SCK" I L 1750 3250 50
|
||||
F15 "CPU_SPI2_MISO" I L 1750 3350 50
|
||||
F16 "CPU_SPI2_MOSI" I L 1750 3450 50
|
||||
F17 "CPU_SWDIO" I R 3250 4450 50
|
||||
F18 "CPU_SWCLK" I R 3250 4550 50
|
||||
F19 "CPU_UART1_TX" I L 1750 3800 50
|
||||
F20 "CPU_UART1_RX" I L 1750 3900 50
|
||||
F21 "CPU_UART4_TX" I L 1750 4050 50
|
||||
F22 "CPU_UART4_RX" I L 1750 4150 50
|
||||
F23 "CPU_IIC1_SCL" I L 1750 2200 50
|
||||
F24 "CPU_IIC1_SDA" I L 1750 2300 50
|
||||
F25 "CPU_SPI1_SCK" I L 1750 2750 50
|
||||
F26 "CPU_SPI1_MISO" I L 1750 2850 50
|
||||
F27 "CPU_SPI1_MOSI" I L 1750 2950 50
|
||||
F28 "CPU_SPI2_CS" I L 1750 3550 50
|
||||
F29 "CPU_SPI1_CS" I L 1750 3050 50
|
||||
F30 "CPU_FSMC_DA0" I R 3250 1000 50
|
||||
F31 "CPU_FSMC_DA1" I R 3250 1100 50
|
||||
F32 "CPU_FSMC_DA2" I R 3250 1200 50
|
||||
F33 "CPU_FSMC_DA3" I R 3250 1300 50
|
||||
F34 "CPU_FSMC_DA4" I R 3250 1400 50
|
||||
F35 "CPU_FSMC_DA5" I R 3250 1500 50
|
||||
F36 "CPU_FSMC_DA6" I R 3250 1600 50
|
||||
F37 "CPU_FSMC_DA7" I R 3250 1700 50
|
||||
F38 "CPU_FSMC_DA8" I R 3250 1800 50
|
||||
F39 "CPU_FSMC_DA9" I R 3250 1900 50
|
||||
F40 "CPU_FSMC_DA10" I R 3250 2000 50
|
||||
F41 "CPU_FSMC_DA11" I R 3250 2100 50
|
||||
F42 "CPU_FSMC_DA12" I R 3250 2200 50
|
||||
F43 "CPU_FSMC_D13" I R 3250 2300 50
|
||||
F44 "CPU_FSMC_D14" I R 3250 2400 50
|
||||
F45 "CPU_FSMC_D15" I R 3250 2500 50
|
||||
F46 "CPU_FSMC_A16" I R 3250 2600 50
|
||||
F47 "CPU_FSMC_A17" I R 3250 2700 50
|
||||
F48 "CPU_FSMC_A18" I R 3250 2800 50
|
||||
F49 "CPU_FSMC_A19" I R 3250 2900 50
|
||||
F50 "CPU_FSMC_A20" I R 3250 3000 50
|
||||
F51 "CPU_FSMC_A21" I R 3250 3100 50
|
||||
F52 "CPU_FSMC_A22" I R 3250 3200 50
|
||||
F53 "CPU_FSMC_A23" I R 3250 3300 50
|
||||
F54 "CPU_FSMC_NWE" I R 3250 3450 50
|
||||
F55 "CPU_FSMC_NOE" I R 3250 3550 50
|
||||
F56 "CPU_FSMC_NE1" I R 3250 3650 50
|
||||
F57 "CPU_PWM_CH1" I L 1750 4400 50
|
||||
F58 "CPU_PWM_CH2" I L 1750 4500 50
|
||||
F59 "CPU_PWM_CH3" I L 1750 4600 50
|
||||
F60 "CPU_PWM_CH4" I L 1750 4700 50
|
||||
F61 "CPU_FSMC_NBL0" I R 3250 3750 50
|
||||
F62 "CPU_FSMC_NBL1" I R 3250 3850 50
|
||||
F63 "CPU_FSMC_NL" I R 3250 3950 50
|
||||
F64 "CPU_FSMC_CLK" I R 3250 4050 50
|
||||
F65 "CPU_FSMC_NWAIT" I R 3250 4150 50
|
||||
F66 "CPU_ENC_CS" I L 1750 3150 50
|
||||
$EndSheet
|
||||
$EndSCHEMATC
|
||||
|
|
|
|||
|
|
@ -14,147 +14,207 @@ Comment3 ""
|
|||
Comment4 ""
|
||||
$EndDescr
|
||||
$Sheet
|
||||
S 8300 3850 2050 2150
|
||||
U 60C2FE2A
|
||||
F0 "Power" 50
|
||||
F1 "Power.sch" 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1000 1000 1950 2550
|
||||
U 60C2FDBB
|
||||
F0 "MCU" 50
|
||||
F1 "MCU.sch" 50
|
||||
F2 "CPU_DAC0" I L 1000 1150 50
|
||||
F3 "CPU_DAC1" I L 1000 1250 50
|
||||
F4 "CPU_ADC1" I L 1000 1500 50
|
||||
F5 "CPU_ADC2" I L 1000 1600 50
|
||||
F6 "CPU_ADC3" I L 1000 1700 50
|
||||
F7 "CPU_ADC4" I L 1000 1800 50
|
||||
F8 "CPU_ADC0" I L 1000 1400 50
|
||||
F9 "CPU_ADC5" I L 1000 1900 50
|
||||
F10 "CPU_ADC6" I L 1000 2000 50
|
||||
F11 "CPU_ADC7" I L 1000 2100 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 2250 4300 650 1000
|
||||
U 60E4702B
|
||||
F0 "Ethernet" 50
|
||||
F1 "Ethernet.sch" 50
|
||||
F2 "POE_VC+" I L 2250 5200 50
|
||||
F3 "POE_VC-" I L 2250 5100 50
|
||||
F4 "ENC_SPI_SCK" I L 2250 4900 50
|
||||
F5 "ENC_SPI_MOSI" I L 2250 4800 50
|
||||
F6 "ENC_SPI_MISO" I L 2250 4700 50
|
||||
F7 "ENC_INT" I L 2250 4400 50
|
||||
F8 "ENC_SPI_CS" I L 2250 4600 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 8250 950 600 1200
|
||||
S 7500 950 600 1200
|
||||
U 60FB17F2
|
||||
F0 "High_Speed_ADC" 50
|
||||
F1 "High_Speed_ADC.sch" 50
|
||||
F2 "ADC_IN" I L 8250 1050 50
|
||||
F3 "ADC_CLK" I L 8250 1200 50
|
||||
F4 "ADC_DATA1" I L 8250 1350 50
|
||||
F5 "ADC_DATA2" I L 8250 1450 50
|
||||
F6 "ADC_DATA3" I L 8250 1550 50
|
||||
F7 "ADC_DATA4" I L 8250 1650 50
|
||||
F8 "ADC_DATA5" I L 8250 1750 50
|
||||
F9 "ADC_DATA6" I L 8250 1850 50
|
||||
F10 "ADC_DATA7" I L 8250 1950 50
|
||||
F11 "ADC_DATA8" I L 8250 2050 50
|
||||
F2 "ADC_IN" I L 7500 1050 50
|
||||
F3 "ADC_CLK" I L 7500 1200 50
|
||||
F4 "ADC_DATA1" I L 7500 1350 50
|
||||
F5 "ADC_DATA2" I L 7500 1450 50
|
||||
F6 "ADC_DATA3" I L 7500 1550 50
|
||||
F7 "ADC_DATA4" I L 7500 1650 50
|
||||
F8 "ADC_DATA5" I L 7500 1750 50
|
||||
F9 "ADC_DATA6" I L 7500 1850 50
|
||||
F10 "ADC_DATA7" I L 7500 1950 50
|
||||
F11 "ADC_DATA8" I L 7500 2050 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 4450 800 1500 5450
|
||||
S 4650 900 1500 5450
|
||||
U 60C0E996
|
||||
F0 "FPGA" 50
|
||||
F1 "FPGA.sch" 50
|
||||
F2 "FPGA_VPP_FAST" I L 4450 4500 50
|
||||
F3 "FPGA_EEM0_0_P" I R 5950 850 50
|
||||
F4 "FPGA_EEM0_0_N" I R 5950 950 50
|
||||
F5 "FPGA_EEM0_7_P" I R 5950 2250 50
|
||||
F6 "FPGA_EEM0_7_N" I R 5950 2350 50
|
||||
F7 "FPGA_EEM0_6_P" I R 5950 2050 50
|
||||
F8 "FPGA_EEM0_6_N" I R 5950 2150 50
|
||||
F9 "FPGA_EEM0_5_P" I R 5950 1850 50
|
||||
F10 "FPGA_EEM0_5_N" I R 5950 1950 50
|
||||
F11 "FPGA_EEM0_4_P" I R 5950 1650 50
|
||||
F12 "FPGA_EEM0_4_N" I R 5950 1750 50
|
||||
F13 "FPGA_EEM0_3_P" I R 5950 1450 50
|
||||
F14 "FPGA_EEM0_3_N" I R 5950 1550 50
|
||||
F15 "FPGA_EEM0_2_P" I R 5950 1250 50
|
||||
F16 "FPGA_EEM0_2_N" I R 5950 1350 50
|
||||
F17 "FPGA_EEM0_1_P" I R 5950 1050 50
|
||||
F18 "FPGA_EEM0_1_N" I R 5950 1150 50
|
||||
F19 "FPGA_EEM1_0_P" I R 5950 2650 50
|
||||
F20 "FPGA_EEM1_0_N" I R 5950 2750 50
|
||||
F21 "FPGA_EEM1_7_P" I R 5950 4050 50
|
||||
F22 "FPGA_EEM1_7_N" I R 5950 4150 50
|
||||
F23 "FPGA_EEM1_6_P" I R 5950 3850 50
|
||||
F24 "FPGA_EEM1_6_N" I R 5950 3950 50
|
||||
F25 "FPGA_EEM1_5_P" I R 5950 3650 50
|
||||
F26 "FPGA_EEM1_5_N" I R 5950 3750 50
|
||||
F27 "FPGA_EEM1_4_P" I R 5950 3450 50
|
||||
F28 "FPGA_EEM1_4_N" I R 5950 3550 50
|
||||
F29 "FPGA_EEM1_3_P" I R 5950 3250 50
|
||||
F30 "FPGA_EEM1_3_N" I R 5950 3350 50
|
||||
F31 "FPGA_EEM1_2_P" I R 5950 3050 50
|
||||
F32 "FPGA_EEM1_2_N" I R 5950 3150 50
|
||||
F33 "FPGA_EEM1_1_P" I R 5950 2850 50
|
||||
F34 "FPGA_EEM1_1_N" I R 5950 2950 50
|
||||
F35 "FPGA_EEM2_0_P" I R 5950 4450 50
|
||||
F36 "FPGA_EEM2_0_N" I R 5950 4550 50
|
||||
F37 "FPGA_EEM2_7_P" I R 5950 5850 50
|
||||
F38 "FPGA_EEM2_7_N" I R 5950 5950 50
|
||||
F39 "FPGA_EEM2_6_P" I R 5950 5650 50
|
||||
F40 "FPGA_EEM2_6_N" I R 5950 5750 50
|
||||
F41 "FPGA_EEM2_5_P" I R 5950 5450 50
|
||||
F42 "FPGA_EEM2_5_N" I R 5950 5550 50
|
||||
F43 "FPGA_EEM2_4_P" I R 5950 5250 50
|
||||
F44 "FPGA_EEM2_4_N" I R 5950 5350 50
|
||||
F45 "FPGA_EEM2_3_P" I R 5950 5050 50
|
||||
F46 "FPGA_EEM2_3_N" I R 5950 5150 50
|
||||
F47 "FPGA_EEM2_2_P" I R 5950 4850 50
|
||||
F48 "FPGA_EEM2_2_N" I R 5950 4950 50
|
||||
F49 "FPGA_EEM2_1_P" I R 5950 4650 50
|
||||
F50 "FPGA_EEM2_1_N" I R 5950 4750 50
|
||||
F51 "FPGA_IIC0_SDA" I R 5950 2550 50
|
||||
F52 "FPGA_IIC0_SCL" I R 5950 2450 50
|
||||
F53 "FPGA_IIC1_SDA" I R 5950 4350 50
|
||||
F54 "FPGA_IIC1_SCL" I R 5950 4250 50
|
||||
F55 "FPGA_IIC2_SDA" I R 5950 6150 50
|
||||
F56 "FPGA_IIC2_SCL" I R 5950 6050 50
|
||||
F57 "FPGA_FSMC_A0" I L 4450 850 50
|
||||
F58 "FPGA_FSMC_A1" I L 4450 950 50
|
||||
F59 "FPGA_FSMC_A2" I L 4450 1050 50
|
||||
F60 "FPGA_FSMC_A3" I L 4450 1150 50
|
||||
F61 "FPGA_FSMC_A4" I L 4450 1250 50
|
||||
F62 "FPGA_FSMC_A5" I L 4450 1350 50
|
||||
F63 "FPGA_FSMC_A6" I L 4450 1450 50
|
||||
F64 "FPGA_FSMC_A7" I L 4450 1550 50
|
||||
F65 "FPGA_FSMC_D0" I L 4450 1650 50
|
||||
F66 "FPGA_FSMC_D1" I L 4450 1750 50
|
||||
F67 "FPGA_FSMC_D2" I L 4450 1850 50
|
||||
F68 "FPGA_FSMC_D3" I L 4450 1950 50
|
||||
F69 "FPGA_FSMC_D4" I L 4450 2050 50
|
||||
F70 "FPGA_FSMC_D5" I L 4450 2150 50
|
||||
F71 "FPGA_FSMC_D6" I L 4450 2250 50
|
||||
F72 "FPGA_FSMC_D7" I L 4450 2350 50
|
||||
F73 "FPGA_FSMC_D8" I L 4450 2450 50
|
||||
F74 "FPGA_FSMC_D9" I L 4450 2550 50
|
||||
F75 "FPGA_FSMC_D10" I L 4450 2650 50
|
||||
F76 "FPGA_FSMC_D11" I L 4450 2750 50
|
||||
F77 "FPGA_FSMC_D12" I L 4450 2850 50
|
||||
F78 "FPGA_FSMC_D13" I L 4450 2950 50
|
||||
F79 "FPGA_FSMC_D14" I L 4450 3050 50
|
||||
F80 "FPGA_FSMC_D15" I L 4450 3150 50
|
||||
F81 "FPGA_CSBSEL0" I L 4450 3500 50
|
||||
F82 "FPGA_CSBSEL1" I L 4450 3600 50
|
||||
F83 "FPGA_SPI_SDO" I L 4450 3700 50
|
||||
F84 "FPGA_SPI_SDI" I L 4450 3800 50
|
||||
F85 "FPGA_SPI_SS" I L 4450 3900 50
|
||||
F86 "FPGA_SPI_SCK" I L 4450 4000 50
|
||||
F87 "FPGA_CDONE" I L 4450 4100 50
|
||||
F88 "FPGA_CRESET" I L 4450 4200 50
|
||||
F2 "FPGA_VPP_FAST" I L 4650 4600 50
|
||||
F3 "FPGA_EEM0_0_P" I R 6150 950 50
|
||||
F4 "FPGA_EEM0_0_N" I R 6150 1050 50
|
||||
F5 "FPGA_EEM0_7_P" I R 6150 2350 50
|
||||
F6 "FPGA_EEM0_7_N" I R 6150 2450 50
|
||||
F7 "FPGA_EEM0_6_P" I R 6150 2150 50
|
||||
F8 "FPGA_EEM0_6_N" I R 6150 2250 50
|
||||
F9 "FPGA_EEM0_5_P" I R 6150 1950 50
|
||||
F10 "FPGA_EEM0_5_N" I R 6150 2050 50
|
||||
F11 "FPGA_EEM0_4_P" I R 6150 1750 50
|
||||
F12 "FPGA_EEM0_4_N" I R 6150 1850 50
|
||||
F13 "FPGA_EEM0_3_P" I R 6150 1550 50
|
||||
F14 "FPGA_EEM0_3_N" I R 6150 1650 50
|
||||
F15 "FPGA_EEM0_2_P" I R 6150 1350 50
|
||||
F16 "FPGA_EEM0_2_N" I R 6150 1450 50
|
||||
F17 "FPGA_EEM0_1_P" I R 6150 1150 50
|
||||
F18 "FPGA_EEM0_1_N" I R 6150 1250 50
|
||||
F19 "FPGA_EEM1_0_P" I R 6150 2750 50
|
||||
F20 "FPGA_EEM1_0_N" I R 6150 2850 50
|
||||
F21 "FPGA_EEM1_7_P" I R 6150 4150 50
|
||||
F22 "FPGA_EEM1_7_N" I R 6150 4250 50
|
||||
F23 "FPGA_EEM1_6_P" I R 6150 3950 50
|
||||
F24 "FPGA_EEM1_6_N" I R 6150 4050 50
|
||||
F25 "FPGA_EEM1_5_P" I R 6150 3750 50
|
||||
F26 "FPGA_EEM1_5_N" I R 6150 3850 50
|
||||
F27 "FPGA_EEM1_4_P" I R 6150 3550 50
|
||||
F28 "FPGA_EEM1_4_N" I R 6150 3650 50
|
||||
F29 "FPGA_EEM1_3_P" I R 6150 3350 50
|
||||
F30 "FPGA_EEM1_3_N" I R 6150 3450 50
|
||||
F31 "FPGA_EEM1_2_P" I R 6150 3150 50
|
||||
F32 "FPGA_EEM1_2_N" I R 6150 3250 50
|
||||
F33 "FPGA_EEM1_1_P" I R 6150 2950 50
|
||||
F34 "FPGA_EEM1_1_N" I R 6150 3050 50
|
||||
F35 "FPGA_EEM2_0_P" I R 6150 4550 50
|
||||
F36 "FPGA_EEM2_0_N" I R 6150 4650 50
|
||||
F37 "FPGA_EEM2_7_P" I R 6150 5950 50
|
||||
F38 "FPGA_EEM2_7_N" I R 6150 6050 50
|
||||
F39 "FPGA_EEM2_6_P" I R 6150 5750 50
|
||||
F40 "FPGA_EEM2_6_N" I R 6150 5850 50
|
||||
F41 "FPGA_EEM2_5_P" I R 6150 5550 50
|
||||
F42 "FPGA_EEM2_5_N" I R 6150 5650 50
|
||||
F43 "FPGA_EEM2_4_P" I R 6150 5350 50
|
||||
F44 "FPGA_EEM2_4_N" I R 6150 5450 50
|
||||
F45 "FPGA_EEM2_3_P" I R 6150 5150 50
|
||||
F46 "FPGA_EEM2_3_N" I R 6150 5250 50
|
||||
F47 "FPGA_EEM2_2_P" I R 6150 4950 50
|
||||
F48 "FPGA_EEM2_2_N" I R 6150 5050 50
|
||||
F49 "FPGA_EEM2_1_P" I R 6150 4750 50
|
||||
F50 "FPGA_EEM2_1_N" I R 6150 4850 50
|
||||
F51 "FPGA_IIC0_SDA" I R 6150 2650 50
|
||||
F52 "FPGA_IIC0_SCL" I R 6150 2550 50
|
||||
F53 "FPGA_IIC1_SDA" I R 6150 4450 50
|
||||
F54 "FPGA_IIC1_SCL" I R 6150 4350 50
|
||||
F55 "FPGA_IIC2_SDA" I R 6150 6250 50
|
||||
F56 "FPGA_IIC2_SCL" I R 6150 6150 50
|
||||
F57 "FPGA_FSMC_A0" I L 4650 950 50
|
||||
F58 "FPGA_FSMC_A1" I L 4650 1050 50
|
||||
F59 "FPGA_FSMC_A2" I L 4650 1150 50
|
||||
F60 "FPGA_FSMC_A3" I L 4650 1250 50
|
||||
F61 "FPGA_FSMC_A4" I L 4650 1350 50
|
||||
F62 "FPGA_FSMC_A5" I L 4650 1450 50
|
||||
F63 "FPGA_FSMC_A6" I L 4650 1550 50
|
||||
F64 "FPGA_FSMC_A7" I L 4650 1650 50
|
||||
F65 "FPGA_FSMC_D0" I L 4650 1750 50
|
||||
F66 "FPGA_FSMC_D1" I L 4650 1850 50
|
||||
F67 "FPGA_FSMC_D2" I L 4650 1950 50
|
||||
F68 "FPGA_FSMC_D3" I L 4650 2050 50
|
||||
F69 "FPGA_FSMC_D4" I L 4650 2150 50
|
||||
F70 "FPGA_FSMC_D5" I L 4650 2250 50
|
||||
F71 "FPGA_FSMC_D6" I L 4650 2350 50
|
||||
F72 "FPGA_FSMC_D7" I L 4650 2450 50
|
||||
F73 "FPGA_FSMC_D8" I L 4650 2550 50
|
||||
F74 "FPGA_FSMC_D9" I L 4650 2650 50
|
||||
F75 "FPGA_FSMC_D10" I L 4650 2750 50
|
||||
F76 "FPGA_FSMC_D11" I L 4650 2850 50
|
||||
F77 "FPGA_FSMC_D12" I L 4650 2950 50
|
||||
F78 "FPGA_FSMC_D13" I L 4650 3050 50
|
||||
F79 "FPGA_FSMC_D14" I L 4650 3150 50
|
||||
F80 "FPGA_FSMC_D15" I L 4650 3250 50
|
||||
F81 "FPGA_CSBSEL0" I L 4650 3600 50
|
||||
F82 "FPGA_CSBSEL1" I L 4650 3700 50
|
||||
F83 "FPGA_SPI_SDO" I L 4650 3800 50
|
||||
F84 "FPGA_SPI_SDI" I L 4650 3900 50
|
||||
F85 "FPGA_SPI_SS" I L 4650 4000 50
|
||||
F86 "FPGA_SPI_SCK" I L 4650 4100 50
|
||||
F87 "FPGA_CDONE" I L 4650 4200 50
|
||||
F88 "FPGA_CRESET" I L 4650 4300 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 2950 6250 650 1000
|
||||
U 60E4702B
|
||||
F0 "Ethernet" 50
|
||||
F1 "Ethernet.sch" 50
|
||||
F2 "POE_VC+" I L 2950 7150 50
|
||||
F3 "POE_VC-" I L 2950 7050 50
|
||||
F4 "ENC_SPI_SCK" I L 2950 6850 50
|
||||
F5 "ENC_SPI_MOSI" I L 2950 6750 50
|
||||
F6 "ENC_SPI_MISO" I L 2950 6650 50
|
||||
F7 "ENC_INT" I L 2950 6350 50
|
||||
F8 "ENC_SPI_CS" I L 2950 6550 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1700 6300 750 800
|
||||
U 60C2FE2A
|
||||
F0 "Power" 50
|
||||
F1 "Power.sch" 50
|
||||
F2 "POE_VC+" I L 1700 6450 50
|
||||
F3 "POE_VC-" I L 1700 6550 50
|
||||
F4 "POE_AT_EVENT" I L 1700 6750 50
|
||||
F5 "POE_SRC_Status" I L 1700 6850 50
|
||||
F6 "POE_CPU_RESET" I L 1700 6950 50
|
||||
$EndSheet
|
||||
$Sheet
|
||||
S 1750 900 1500 3950
|
||||
U 60C2FDBB
|
||||
F0 "MCU" 50
|
||||
F1 "MCU.sch" 50
|
||||
F2 "CPU_DAC0" I L 1750 1000 50
|
||||
F3 "CPU_DAC1" I L 1750 1100 50
|
||||
F4 "CPU_ADC1" I L 1750 1400 50
|
||||
F5 "CPU_ADC2" I L 1750 1500 50
|
||||
F6 "CPU_ADC3" I L 1750 1600 50
|
||||
F7 "CPU_ADC4" I L 1750 1700 50
|
||||
F8 "CPU_ADC0" I L 1750 1300 50
|
||||
F9 "CPU_ADC5" I L 1750 1800 50
|
||||
F10 "CPU_ADC6" I L 1750 1900 50
|
||||
F11 "CPU_ADC7" I L 1750 2000 50
|
||||
F12 "CPU_IIC2_SCL" I L 1750 2450 50
|
||||
F13 "CPU_IIC2_SDA" I L 1750 2550 50
|
||||
F14 "CPU_SPI2_SCK" I L 1750 3250 50
|
||||
F15 "CPU_SPI2_MISO" I L 1750 3350 50
|
||||
F16 "CPU_SPI2_MOSI" I L 1750 3450 50
|
||||
F17 "CPU_SWDIO" I R 3250 4450 50
|
||||
F18 "CPU_SWCLK" I R 3250 4550 50
|
||||
F19 "CPU_UART1_TX" I L 1750 3800 50
|
||||
F20 "CPU_UART1_RX" I L 1750 3900 50
|
||||
F21 "CPU_UART4_TX" I L 1750 4050 50
|
||||
F22 "CPU_UART4_RX" I L 1750 4150 50
|
||||
F23 "CPU_IIC1_SCL" I L 1750 2200 50
|
||||
F24 "CPU_IIC1_SDA" I L 1750 2300 50
|
||||
F25 "CPU_SPI1_SCK" I L 1750 2750 50
|
||||
F26 "CPU_SPI1_MISO" I L 1750 2850 50
|
||||
F27 "CPU_SPI1_MOSI" I L 1750 2950 50
|
||||
F28 "CPU_SPI2_CS" I L 1750 3550 50
|
||||
F29 "CPU_SPI1_CS" I L 1750 3050 50
|
||||
F30 "CPU_FSMC_DA0" I R 3250 1000 50
|
||||
F31 "CPU_FSMC_DA1" I R 3250 1100 50
|
||||
F32 "CPU_FSMC_DA2" I R 3250 1200 50
|
||||
F33 "CPU_FSMC_DA3" I R 3250 1300 50
|
||||
F34 "CPU_FSMC_DA4" I R 3250 1400 50
|
||||
F35 "CPU_FSMC_DA5" I R 3250 1500 50
|
||||
F36 "CPU_FSMC_DA6" I R 3250 1600 50
|
||||
F37 "CPU_FSMC_DA7" I R 3250 1700 50
|
||||
F38 "CPU_FSMC_DA8" I R 3250 1800 50
|
||||
F39 "CPU_FSMC_DA9" I R 3250 1900 50
|
||||
F40 "CPU_FSMC_DA10" I R 3250 2000 50
|
||||
F41 "CPU_FSMC_DA11" I R 3250 2100 50
|
||||
F42 "CPU_FSMC_DA12" I R 3250 2200 50
|
||||
F43 "CPU_FSMC_D13" I R 3250 2300 50
|
||||
F44 "CPU_FSMC_D14" I R 3250 2400 50
|
||||
F45 "CPU_FSMC_D15" I R 3250 2500 50
|
||||
F46 "CPU_FSMC_A16" I R 3250 2600 50
|
||||
F47 "CPU_FSMC_A17" I R 3250 2700 50
|
||||
F48 "CPU_FSMC_A18" I R 3250 2800 50
|
||||
F49 "CPU_FSMC_A19" I R 3250 2900 50
|
||||
F50 "CPU_FSMC_A20" I R 3250 3000 50
|
||||
F51 "CPU_FSMC_A21" I R 3250 3100 50
|
||||
F52 "CPU_FSMC_A22" I R 3250 3200 50
|
||||
F53 "CPU_FSMC_A23" I R 3250 3300 50
|
||||
F54 "CPU_FSMC_NWE" I R 3250 3450 50
|
||||
F55 "CPU_FSMC_NOE" I R 3250 3550 50
|
||||
F56 "CPU_FSMC_NE1" I R 3250 3650 50
|
||||
F57 "CPU_PWM_CH1" I L 1750 4400 50
|
||||
F58 "CPU_PWM_CH2" I L 1750 4500 50
|
||||
F59 "CPU_PWM_CH3" I L 1750 4600 50
|
||||
F60 "CPU_PWM_CH4" I L 1750 4700 50
|
||||
F61 "CPU_FSMC_NBL0" I R 3250 3750 50
|
||||
F62 "CPU_FSMC_NBL1" I R 3250 3850 50
|
||||
F63 "CPU_FSMC_NL" I R 3250 3950 50
|
||||
F64 "CPU_FSMC_CLK" I R 3250 4050 50
|
||||
F65 "CPU_FSMC_NWAIT" I R 3250 4150 50
|
||||
F66 "CPU_ENC_CS" I L 1750 3150 50
|
||||
$EndSheet
|
||||
$EndSCHEMATC
|
||||
|
|
|
|||
Loading…
Reference in New Issue