5432: spellcheck, style

Closes #50

.gitignore

@@ -0,0 +1,9 @@
+*.out
+*.log
+*.aux
+
+_minted-*
+build
+result
+
+images/unsorted

1124.tex

@@ -0,0 +1,307 @@
+\include{preamble.tex}
+\graphicspath{{images/1124}{images}}
+
+\title{1124 Carrier Kasli 2.0}
+\author{M-Labs Limited}
+\date{October 2024}
+\revision{Revision 2}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{4 SFP 6Gb/s slots for Ethernet and DRTIO}
+\item{12 EEM ports for daughtercards}
+\item{4 MMCX clock outputs}
+\item{Xilinx Artix-7 FPGA core}
+\item{DDR3 SDRAM}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Run ARTIQ kernels}
+\item{Communicate with the host}
+\item{Control other Sinara EEM cards}
+\item{Distributed Real-Time I/O}
+\end{itemize}
+
+\section{General Description}
+The 1124 Kasli 2.0 Carrier card is an 8hp EEM module, designed to run ARTIQ kernels sent from a host machine over the network. It supports up to 12 EEM connections to other EEM cards in the ARTIQ-Sinara family and up four SFP connections, used for comunications with other carriers and/or Ethernet.
+
+Real-time control of EEM daughtercards is implemented using the ARTIQ RTIO system. 1ns temporal resolution can be achieved for TTL events.
+
+4 SFP 6Gb/s slots are provided. One may be used for Ethernet, which supports communication with a host machine. Remaining slots can be used by the ARTIQ Distributed Real-Time Input/Output (DRTIO) system, which allows for the use of additional core devices (e.g. Kasli 2.0, Kasli-SoC) as satellite cards, capable of running subkernels or distributing commands from the \mbox{DRTIO} master.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{1.15}{
+    \begin{circuitikz}[european, every label/.append style={align=center}]
+
+        \begin{scope}[]
+
+            % Draw the FPGA
+            \draw (0, 0) node[twoportshape, t={FPGA}, circuitikz/bipoles/twoport/height=1.5, circuitikz/bipoles/twoport/width=1.2, scale=1] (fpga) {};
+
+            % External clock for RTIO, west of the FPGA
+            \draw [color=white, text=black] (-3.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (ext_clk) {};
+            \node [label=left:\tiny{EXT CLK}] at (-2.65, 0) {};
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=-40cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \draw [-latexslim] (ext_clk) -- (fpga.west);
+
+            % USB Mirco B port with USB-UART converter, north west of the FPGA
+            \draw (-3.2, 1.2) node[twoportshape, t={USB Micro B}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (usb) {};
+            \draw (-2, 1.2) node[twoportshape, t={\fourcm{USB-UART}{Converter}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (uart) {};
+            \draw [latexslim-latexslim] (usb.north) -- (uart.south);
+            \draw [latexslim-latexslim] (uart.north) -- (-1.3, 1.2) -- (-1.3, 0.4) -- (-0.85, 0.4);
+
+            % 4-SFP cage, south west of the FPGA
+            \draw (-3.4, -0.8) node[twoportshape, t={SFP 0}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp0) {};
+            \draw (-3, -0.8) node[twoportshape, t={SFP 1}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp1) {};
+            \draw (-3.4, -1.5) node[twoportshape, t={SFP 2}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp2) {};
+            \draw (-3, -1.5) node[twoportshape, t={SFP 3}, circuitikz/bipoles/twoport/height=0.6, circuitikz/bipoles/twoport/width=1, scale=0.5, rotate=-90] (sfp3) {};
+            \draw [latexslim-latexslim] (-2.8, -1.15) -- (-2.2, -1.15) -- (-2.2, -0.4) -- (-0.85, -0.4);
+
+            % Clock signal cleaning path, south of the FPGA,
+            % clock signal loop from the south west to the south east
+            \draw (-0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Multiplier}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_mul) {};
+            \draw (0.8, -2.1) node[twoportshape, t={\fourcm{Clock}{Buffer}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (clk_buf) {};
+            \draw [-latexslim] (-0.85, -0.8) -- (-1.6, -0.8) -- (-1.6, -1.9) -- (-1.05, -1.9);
+            % % A dashed path from EXT CLK to CDR CLK
+            \draw [dashed, -latexslim] (fpga.west) -- (-0.6, 0) -- (-0.6, -0.8) -- (-0.85, -0.8);
+            % % Internal oscillator for the RTIO clock
+            \draw (-2.2, -2.3) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=1, scale=0.5] (rtio_osc) {};
+            \draw [-latexslim] (rtio_osc.east) -- (-1.05, -2.3);
+            \draw [-latexslim] (clk_mul.north) -- (clk_buf.south);
+            \draw [-latexslim] (clk_buf.north) -- (1.6, -2.1) -- (1.6, -0.4) -- (0.85, -0.4);
+            % % MMCX output
+            \draw [color=white, text=black] (2.75, -1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx0) {};
+            \draw [color=white, text=black] (2.75, -1.4) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx1) {};
+            \draw [color=white, text=black] (2.75, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx2) {};
+            \draw [color=white, text=black] (2.75, -2.1) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (mmcx3) {};
+            \node [label=right:\tiny{MMCX 0}] at (2.3, -1.05) {};
+            \node [label=right:\tiny{MMCX 1}] at (2.3, -1.4) {};
+            \node [label=right:\tiny{MMCX 2}] at (2.3, -1.75) {};
+            \node [label=right:\tiny{MMCX 3}] at (2.3, -2.1) {};
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-30cm, yshift=-35cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-25cm, yshift=-35cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-20cm, yshift=-35cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-15cm, yshift=-35cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+
+            \draw [-latexslim] (1.6, -1.05) -- (mmcx0);
+            \draw [-latexslim] (1.6, -1.4) -- (mmcx1);
+            \draw [-latexslim] (1.6, -1.75) -- (mmcx2);
+            \draw [-latexslim] (1.6, -2.1) -- (mmcx3);
+
+            % Memory modules, north of the FPGA
+            \draw (-0.55, 2.4) node[twoportshape, t={\fourcm{SPI}{Flash}}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (spi_flash) {};
+            \draw (0.55, 2.4) node[twoportshape, t={SDRAM}, circuitikz/bipoles/twoport/width=1.3, scale=0.5] (sdram) {};
+            \draw [latexslim-latexslim] (spi_flash.south) -- (-0.55, 1.05);
+            \draw [latexslim-latexslim] (sdram.south) -- (0.55, 1.05);
+
+            % EEM connectors x12, horizontally located at y=0.4
+            \draw (2, 1.8) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eem0) {};
+            \node at (2.4, 1.8)[circle,fill,inner sep=0.7pt]{};
+            \node at (2.6, 1.8)[circle,fill,inner sep=0.7pt]{};
+            \node at (2.8, 1.8)[circle,fill,inner sep=0.7pt]{};
+            \draw (3.2, 1.8) node[twoportshape, t={EEM Port 11}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eem11) {};
+            \draw [decorate, decoration = {brace}] (3.4, 1.1) --  (1.8, 1.1);
+            \draw [latexslim-latexslim] (2.6, 1) -- (2.6, 0.4) -- (0.85, 0.4);
+        \end{scope}
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2in]{photo1124.jpg}
+    \caption{Kasli 2.0 card}
+\end{figure}
+
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[angle=90,height=0.9in]{Kasli_FP.pdf}
+    \caption{Kasli 2.0 front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{Kasli 2.0}{https://github.com/sinara-hw/Kasli}
+
+\section{Electrical Specifications}
+External clock parameters are derived based on the internal termination specified in
+UG471\footnote{\label{ug471}\url{https://docs.xilinx.com/v/u/en-US/ug471\_7Series\_SelectIO}}
+and the voltage range specified in
+DS181\footnote{\label{ds181}\url{https://docs.xilinx.com/v/u/en-US/ds181\_Artix\_7\_Data\_Sheet}}. These figures account for the insertion loss of the RF transformer (TC2-1TX+\footnote{\label{rf_trans}\url{https://www.minicircuits.com/pdfs/TC2-1TX+.pdf}}).
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Recommended Operating Conditions}
+\begin{tabularx}{0.85\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Clock input & & & & &\\
+    \hspace{3mm} Input frequency & & 125 & & MHz & Si5324 synthesizer bypassed \\
+    \cline{2-6}
+    % 100R termination & 100/350/600 mV differential input after the transformer.
+    & \multicolumn{3}   {c|}{10/100/125} & MHz & RTIO clock synthesized from input \\
+    \cline{2-6}
+    \hspace{3mm} Power & -9 & 1.5 & 5.5 & dBm & \\
+    \hline
+    Power supply rating & \multicolumn{4}{c|}{12V, 5A} & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+Power is to be supplied through the barrel connector in the front panel, size 5.5 mm OD, 2.5 mm ID, and is passed on to daughtercards through the EEM connections. Locking barrel connectors are supported.
+
+\section{FPGA}
+
+Kasli 2.0 features an XC7A100T-3FGG484E Xilinx Artix-7 FPGA to facilitate reconfigurable high-speed real-time control of inputs and outputs. Most commonly, this FPGA is flashed with binaries compiled from the ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) control system, which equips the carrier board with specialized gateware for handling other Sinara EEMs and an on-FPGA CPU for running ARTIQ experiment \mbox{kernels}.
+
+ARTIQ is open-source and can be found in the repository \url{https://github.com/m-labs/artiq}. Orders of Sinara hardware are normally accompanied with precompiled binaries. Long-term support for ARTIQ systems can also be purchased.
+
+A micro-USB located on the front panel is equipped for JTAG, I2C, and UART serial output. The serial interface runs at 115200bps 8-N-1.
+
+\subsection{Note on distributed RTIO (DRTIO)}
+
+DRTIO is the time and data transfer system that allows ARTIQ RTIO channels to be distributed among several core device carrier boards, synchronized and controlled by a central core device. The system itself is more fully described in the ARTIQ documentation\footnote{\label{manual-drtio}\url{https://m-labs.hk/artiq/manual/drtio.html}}. With ARTIQ firmware/gateware, supported core devices, including Kasli 2.0, can take one of three roles:
+\begin{enumerate}
+    \item \textbf{Master} \\
+    The DRTIO master is unique in a DRTIO system. It requires a direct network connection to the host machine. It may make downstream connections to satellites. It controls its own local RTIO channels and the downstream DRTIO satellite(s).
+    \item \textbf{Satellite} \\
+    Any other core devices in a DRTIO system are DRTIO satellites. They require an upstream connection to one other core device, master or satellite, through which communications will ultimately be chained to the master. They may make further downstream connections to other satellites. They may control RTIO channels through subkernels or simply pass on communications from the master.
+    \item \textbf{Standalone}\\
+    When run in a non-distributed ARTIQ configuration, with a single central core device but no satellites, that core device is instead known as standalone.
+\end{enumerate}
+
+\section{Communication Interfaces}
+
+Communication between devices is implemented using 1000Base-T small form-factor pluggable (SFP) interfaces. Four are available on the Kasli 2.0. Appropriate SFP transceivers must be plugged inside the corresponding SFP cages. Each SFP connector possesses an indicator LED.
+
+\subsection{Upstream connection}
+
+A Kasli 2.0 board must acquire an upstream connection through the \texttt{SFP0} slot.
+
+\begin{itemize}
+    \item \textbf{Standalone/Master} \\
+    An Ethernet-capable SFP transceiver should be inserted into the \texttt{SFP0} slot. Typically, a 10000Base-X RJ45 SFP module is used, with an network-connected Ethernet cable attached to the module.
+    \item \textbf{Satellite} \\
+    The \texttt{SFP0} port should be connected to one of the free SFP slots on an upstream core device, using a cable connection with SFP transceivers.
+\end{itemize}
+
+\subsection{Downstream connection}
+Kasli 2.0 supports up to 3 DRTIO satellite connections per device. Any of the 3 downstream SFP ports (i.e. \texttt{SFP1}, \texttt{SFP2}, \texttt{SFP3}) may be used.
+
+\section{Clock Routing}
+\subsection{Standalone/Master}
+The RTIO clock is typically synthesized by the Si5324 clock multiplier and distributed by the ADCLK948 clock fanout buffer to both the FPGA and the MMCX connectors. Alternatively, an external reference can be supplied through the front panel SMA connector. It is then buffered in the FPGA and sent to the Si5324 for clock synthesis. Kasli 2.0 supports a set of RTIO clock options:
+\begin{table}[H]
+    \centering
+    \begin{tabular}{|c|c|c|}
+    \hline
+    RTIO frequency           & Configuration          & Clock generation                                                \\ \hline
+    100 MHz                  & \texttt{int\char`_100}               & internal crystal oscillator using PLL, 100 MHz output           \\ \hline
+    \multirow{4}{*}{125 MHz} & \texttt{int\char`_125}               & internal crystal oscillator using PLL, 125 MHz output (default) \\ \cline{2-3}
+                             & \texttt{ext0\char`_synth0\char`_10to125}  & external 10 MHz reference using PLL, 125 MHz output             \\ \cline{2-3}
+                             & \texttt{ext0\char`_synth0\char`_100to125} & external 100 MHz reference using PLL, 125 MHz output            \\ \cline{2-3}
+                             & \texttt{ext0\char`_synth0\char`_125to125} & external 125 MHz reference using PLL, 125 MHz output            \\ \hline
+    150 MHz                  & \texttt{int\char`_150}               & internal crystal oscillator using PLL, 150 MHz output           \\ \hline
+    \end{tabular}
+    \end{table}
+
+The clock synthesizer may also be bypassed, using the \texttt{ext0\char`_bypass} option, which will accept a RTIO clock directly supplied to the SMA connector. The resulting signal is then routed to both the RTIO system and downstream satellites.
+
+Clocking options in a running system should be configured by setting the value of the \texttt{rtio\char`_clock} key to the desired configuration through \texttt{artiq\char`_coremgmt}. For example, a RTIO frequency of 125MHz will be synthesized from an external 10 MHz signal after issuing the following command:
+
+\begin{minted}{bash}
+    artiq_coremgmt config write -s rtio_clock ext0_synth0_10to125
+\end{minted}
+
+and rebooting.
+
+\subsection{Satellite}
+The RTIO clock is recovered from the SFP transceiver connected to the upstream device. The resulting signal is then cleaned up by the Si5324 and routed to both the RTIO system and downstream satellites.
+
+\subsection{WRPLL}
+
+Kasli 2.0 can be configured to use WRPLL, a clock recovery method making use of White Rabbit's DDMTD (Digital Dual Mixer Time Difference) and the card's Si549 oscillators, both to lock the main RTIO clock and to lock satellite clocks to master.
+
+\section{User LEDs}
+
+Kasli 2.0 supplies three user LEDs for debugging purposes. Two are located on the front panel. The third is located on the PCB itself, beside the SFP cage. An additional ERR LED on the front panel is used by ARTIQ firmware to indicate a runtime panic.
+
+\newpage
+
+\codesection{Kasli 2.0 1124 carrier}
+
+\subsection{Direct Memory Access (DMA)}
+Instead of directly emitting RTIO events, sequences of RTIO events can be recorded in advance and stored in the local SDRAM. The event sequence can then be replayed at a specified timestamp. This is of special advantage in cases where RTIO events are too closely placed to be generated as they are executed, as events can be replayed at a higher speed than the on-FPGA CPU alone is capable of.
+
+The following example records an LED event sequence and replays it twice consecutively using \texttt{CoreDMA}. When run, the LED should blink twice.
+
+\inputcolorboxminted{firstline=10,lastline=29}{examples/dma.py}
+
+Stored waveforms can be referenced and replayed in different kernels, but cannot be retrieved and must be regenerated if the core device is rebooted.
+
+\newpage
+
+\subsection{Dataset manipulation with core device cache}
+Experiments may require values computed or found in previously executed kernels. To avoid invoking an RPC or sacrificing the pre-computation in \texttt{prepare()} stage, data can be stored in the core device cache.
+
+The following code snippets describe two experiments, in which the data from the first experiment is cached. The data is then retrieved and printed in hexadecimal form in the second experiment.
+
+\inputcolorboxminted{firstline=9,lastline=16}{examples/cache.py}
+\inputcolorboxminted{firstline=24,lastline=35}{examples/cache.py}
+
+Similar to DMA, cached data is no longer retrievable once the core device has been rebooted.
+
+\ordersection{1124 Carrier Kasli 2.0}
+
+\finalfootnote
+
+\end{document}

2118-2128.tex

@@ -0,0 +1,468 @@
+\input{preamble.tex}
+\graphicspath{{images/2118-2128}{images}}
+
+\title{2118 BNC-TTL / 2128 SMA-TTL}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 2}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{8 TTL channels}
+\item{Input- and output-capable}
+\item{Galvanically isolated}
+\item{3ns minimum pulse width}
+\item{BNC or SMA connectors}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Photon counting}
+\item{External equipment trigger}
+\item{Optical shutter control}
+\end{itemize}
+
+\section{General Description}
+
+The 2118 BNC-TTL card is an 8hp EEM module; the 2128 SMA-TTL is a 4hp EEM module. Both TTL cards add general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+Each card provides two banks of four digital channels, for a total of eight digital channels, with respectively either BNC (2118) or SMA (2128) connectors. Each bank possesses individual ground isolation. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
+
+Each channel supports 50\textOmega~terminations, individually controllable using DIP switches. Outputs tolerate short circuits indefinitely.
+
+Both cards are capable of a minimum pulse width of 3ns.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.88}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        \begin{scope}[yshift=1.3cm]
+
+            \draw[color=white, text=black] (-0.1,0) node[twoportshape,t={IO 0}, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (io0) {};
+            \draw[color=white, text=black] (-0.1,-0.7) node[twoportshape,t={IO 1}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io1) {};
+            \draw[color=white, text=black] (-0.1,-1.4) node[twoportshape,t={IO 2}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io2) {};
+            \draw[color=white, text=black] (-0.1,-2.1) node[twoportshape,t={IO 3}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io3) {};
+
+            \node [label={[xshift=-0.18cm, yshift=-0.305cm]\tiny{IO 0}}] {};
+            \node [label={[xshift=-0.18cm, yshift=-0.97cm]\tiny{IO 1}}] {};
+            \node [label={[xshift=-0.18cm, yshift=-1.64cm]\tiny{IO 2}}] {};
+            \node [label={[xshift=-0.18cm, yshift=-2.302cm]\tiny{IO 3}}] {};
+
+            % draw female SMA_0,1,2,3
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+
+            \draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus1) {};
+
+            \draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso1) {};
+            \draw (3.05,-0.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso2) {};
+            \draw (3.05,-1.4) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso3) {};
+            \draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso4) {};
+            \draw (3.05,-2.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso1) {};
+
+            \draw (4.5,-1.15) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds1) {};
+
+            \draw (6.8,-0.9) -- ++(0.00001,0) node[twoportshape, anchor=left, t={EEM port}, circuitikz/bipoles/twoport/width=6, scale=0.6, rotate=-90] (kasli) {} ;
+            \draw (0.8,-3.5) node[twoportshape,t=\fourcm{Per-bank \phantom{spac} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
+            \draw (3.05,-3.5) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
+
+            \draw (5.68,-2.3) node[twoportshape,t=EEPROM, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom) {};
+
+            \draw (0.8,-2.7) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
+
+            % Termination Switch 1,2,3,4
+            \begin{scope}[xshift=0.9cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+                \draw (0.4,0) to[short,-o](0.75,0);
+                \draw (0.78,0)-- +(30:0.46);
+                \draw (1.25,0)to[short,o-](1.6,0);
+            \end{scope}
+            \begin{scope}[xshift=1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+                \draw (0.4,0) to[short,-o](0.75,0);
+                \draw (0.78,0)-- +(30:0.46);
+                \draw (1.25,0)to[short,o-](1.6,0);
+            \end{scope}
+            \begin{scope}[xshift=1.1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+                \draw (0.4,0) to[short,-o](0.75,0);
+                \draw (0.78,0)-- +(30:0.46);
+                \draw (1.25,0)to[short,o-](1.6,0);
+            \end{scope}
+            \begin{scope}[xshift=1.2cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+                \draw (0.4,0) to[short,-o](0.75,0);
+                \draw (0.78,0)-- +(30:0.46);
+                \draw (1.25,0)to[short,o-](1.6,0);
+            \end{scope}
+
+        \end{scope}
+
+        % I/O Switch 1, 2
+        \begin{scope}[xshift=1.2cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.32cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+
+        \draw (0.8,-3.05) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
+
+        % Termination Switch 5,6,7,8
+        \begin{scope}[xshift=0.9cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.2cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+
+        % channel 5,6,7,8
+        \begin{scope}[yshift=-3.6cm]
+            \draw[color=white, text=black]  (-0.1,0) node[twoportshape,t={IO 4}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io4) {};
+            \draw[color=white, text=black]  (-0.1,-0.7) node[twoportshape,t={IO 5}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io5) {};
+            \draw[color=white, text=black]  (-0.1,-1.4) node[twoportshape,t={IO 6}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io6) {};
+            \draw[color=white, text=black]  (-0.1,-2.1) node[twoportshape,t={IO 7}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io7) {};
+
+            \node [label={[xshift=-0.18cm, yshift=-0.305cm]\tiny{IO 4}}] {};
+            \node [label={[xshift=-0.18cm, yshift=-0.97cm]\tiny{IO 5}}] {};
+            \node [label={[xshift=-0.18cm, yshift=-1.64cm]\tiny{IO 6}}] {};
+            \node [label={[xshift=-0.18cm, yshift=-2.302cm]\tiny{IO 7}}] {};
+
+            % draw female SMA 4,5,6,7
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+
+
+            \draw (1.6,-1.05) node[twoportshape,t={IO Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus2) {};
+
+            \draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso5) {};
+            \draw (3.05,-0.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso6) {};
+            \draw (3.05,-1.4) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso7) {};
+            \draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso8) {};
+            \draw (3.05,0.6) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso2) {};
+
+            \draw (4.5,-1.05) node[twoportshape,t=\fourcm{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds2) {};
+
+        \end{scope}
+
+        % Drawing Connections
+        \draw [latexslim-latexslim] (io0.east) -- ++(1,0);
+        \draw [latexslim-latexslim] (io1.east) -- ++(1,0);
+        \draw [latexslim-latexslim] (io2.east) -- ++(1,0);
+        \draw [latexslim-latexslim] (io3.east) -- ++(1,0);
+        \draw [latexslim-latexslim] (io4.east) -- ++(1,0);
+        \draw [latexslim-latexslim] (io5.east) -- ++(1,0);
+        \draw [latexslim-latexslim] (io6.east) -- ++(1,0);
+        \draw [latexslim-latexslim] (io7.east) -- ++(1,0);
+
+        \draw [latexslim-latexslim] (iso1.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso2.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso3.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso4.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso1.east) -- ++(0.69,0);
+        \draw [latexslim-latexslim] (iso2.east) -- ++(0.69,0);
+        \draw [latexslim-latexslim] (iso3.east) -- ++(0.69,0);
+        \draw [latexslim-latexslim] (iso4.east) -- ++(0.69,0);
+
+        \draw [latexslim-latexslim] (iso5.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso6.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso7.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso8.west) -- ++(-0.72,0) ;
+        \draw [latexslim-latexslim] (iso5.east) -- ++(0.7,0);
+        \draw [latexslim-latexslim] (iso6.east) -- ++(0.7,0);
+        \draw [latexslim-latexslim] (iso7.east) -- ++(0.7,0);
+        \draw [latexslim-latexslim] (iso8.east) -- ++(0.7,0);
+
+        \draw [latexslim-] (eeprom.south) -- ++(0,-0.95);
+
+        \draw [latexslim-latexslim] (lvds1.north) -- ++(1.61,0);
+        \draw [latexslim-latexslim] (lvds2.north) -- ++(1.62,0);
+        \draw [latexslim-latexslim] (i2c.east) -- ++(2.77,0);
+        \draw [latexslim-] (i2c.west) -- (ioswitch.east) ;
+
+        \draw [-latexslim] (i2c.north east) -- (lvds1.south east);
+        \draw [-latexslim] (i2c.south east) -- (lvds2.south west);
+
+        \draw [-latexslim] (i2ciso1.west) -- (bus1.north east);
+        \draw [thin] [-latexslim] (i2c.north) -- (i2ciso1.south);
+
+        \draw [-latexslim] (i2ciso2.west) -- (bus2.north west);
+        \draw [thin] [-latexslim] (i2c.south) -- (i2ciso2.north);
+
+
+        % termination switch connection
+        \draw (0.65,-1.18) -- ++(0,2.47) ;
+        \draw (0.75,-1.18) -- ++(0,1.77) ;
+        \draw (0.85,-1.18) -- ++(0,1.07) ;
+        \draw (0.95,-1.18) -- ++(0,0.37) ;
+
+        \draw (0.65,-3.25) -- ++(0,-2.45) ;
+        \draw (0.75,-3.25) -- ++(0,-1.75) ;
+        \draw (0.85,-3.25) -- ++(0,-1.05) ;
+        \draw (0.95,-3.25) -- ++(0,-0.35) ;
+
+        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(io0) (i2ciso1.south west)] (box1) {};
+        \node[fill=white, rotate=-90] at (box1.west) {GND BANK 1};
+        \node[fill=white,above] at (box1.north) {\tiny{Either all 4 channels are inputs or all 4 channels are outputs }};
+
+
+        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(io4)(termswitch2) (iso8.south west)] (box2) {};
+        \node[fill=white, rotate=-90] at (box2.west) {GND BANK 2};
+        \node[fill=white,below] at (box2.south) {\tiny{Either all 4 channels are inputs or all 4 channels are outputs }};
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=1.8in]{photo2118-2128.jpg }
+    \caption{BNC-TTL and SMA-TTL cards}%
+    \includegraphics[angle=90, height=0.7in]{DIO_BNC_FP.jpg}
+    \includegraphics[angle=90, height=0.4in]{DIO_SMA_FP.jpg}
+    \caption{BNC-TTL and SMA-TTL front panels}%
+    \label{fig:example}%
+\end{figure}
+
+\onecolumn
+
+\sourcesectiond{2118 BNC-TTL}{2128 SMA-TTL}{https://github.com/sinara-hw/DIO_BNC}{https://github.com/sinara-hw/DIO_SMA}
+
+\section{Electrical Specifications}
+All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
+Specifications were derived based on the datasheets of the bus transceiver IC (SN74BCT25245DW\footnote{\label{transceiver}\url{https://www.ti.com/lit/ds/symlink/sn74bct25245.pdf}}) and the isolator IC (SI8651BB-B-IS1\footnote{\label{isolator}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si865x-datasheet.pdf}}). The typical value of minimum pulse width is based on test results\footnote{\label{sinara187}\url{https://github.com/sinara-hw/sinara/issues/187}}.
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Recommended Operating Conditions}
+\begin{tabularx}{\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    High-level input voltage\repeatfootnote{transceiver} & 2 & & 5.5* & V & \\
+    \hline
+    Low-level input voltage\repeatfootnote{transceiver} & -0.5 & & 0.8 & V & \\
+    \hline
+    Input clamp current\repeatfootnote{transceiver} & & & -18 & mA & termination disabled \\
+    \hline
+    High-level output current\repeatfootnote{transceiver} & & & -160 & mA & \\
+    \hline
+    Low-level output current\repeatfootnote{transceiver} & & & 376 & mA & \\
+    \thickhline
+    \multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Electrical Characteristics}
+\begin{tabularx}{\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    High-level output voltage\repeatfootnote{transceiver} & 2 &  &  & V & $I_{OH}$=-160mA \\
+    & 2.7 &  &  & V & $I_{OH}$=-6mA \\
+    \hline
+    Low-level output voltage\repeatfootnote{transceiver} & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
+    &  &  & 0.7 & V & $I_{OL}$=376mA \\
+    \hline
+    Minimum pulse width\repeatfootnote{isolator}\textsuperscript{,}\repeatfootnote{sinara187} & & 3 & 5 & ns & \\
+    \hline
+    Pulse width distortion\repeatfootnote{isolator} & & 0.2 & 4.5 & ns &  \\
+    \hline
+    Peak jitter\repeatfootnote{isolator} & & 350 & & ps &  \\
+    \hline
+    Data rate\repeatfootnote{isolator} & 0 & & 150 & Mbps & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+Minimum pulse width was measured by generating pulses of progressively longer duration through a DDS generator and using them as input for a BNC-TTL card. The input BNC-TTL card was connected to another BNC-TTL card as output. The output signal is measured and shown in Figure \ref{fig:pulsewidth}.
+
+\begin{figure}[ht]
+    \centering
+    \includegraphics[height=3in]{bnc_ttl_min_pulse_width.png}
+    \caption{Minimum pulse width required for BNC-TTL card}
+    \label{fig:pulsewidth}
+\end{figure}
+
+\newpage
+
+The red trace shows the DDS generator input pulses. The blue trace shows the measured signal from the output BNC-TTL. Note that the first red pulse failed to reach the 2.1V threshold required by TTL and was not propagated. The first blue (output) pulse is the result of the second red (input) pulse, of 3ns width, which propagated correctly. 
+
+\section{Configuring IO Direction \& Termination}
+
+IO direction and termination must be configured by setting physical switches on the board. The termination switches are found on the middle-left and the IO direction switches on the middle-right of both cards. Termination switches select between high impedance (\texttt{OFF}) and 50\textOmega~(\texttt{ON}). Note that termination switches are by-channel but IO direction switches are by-bank. 
+
+\begin{itemize}
+    \itemsep0em
+    \item IO direction switch closed (\texttt{ON}) \\
+          Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
+    \item IO direction switch open (OFF) \\
+          The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
+\end{itemize}
+
+\begin{figure}[hbt!]
+    \centering
+    \subfloat[\centering BNC-TTL]{{
+        \includegraphics[height=1.5in]{bnc_ttl_switches.jpg}
+    }}%
+    \subfloat[\centering SMA-TTL]{{
+        \includegraphics[height=1.5in]{sma_ttl_switches.jpg}
+    }}%
+    \caption{Position of switches}%
+\end{figure}
+
+\newpage
+\codesection{2118 BNC-TTL/2128 SMA-TTL cards}
+
+Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
+
+\subsection{One pulse per second}
+The channel should be configured as output in both the gateware and hardware.
+\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
+
+\subsection{Morse code}
+This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
+\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
+
+\newpage
+\subsection{Sub-coarse-RTIO-cycle pulse}
+With the use of ARTIQ RTIO, only one event can be enqueued per \textit{coarse RTIO cycle}, which typically corresponds to 8ns. To emit pulses of less than 8ns, careful timing is needed to ensure that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted during different coarse RTIO cycles.
+
+\inputcolorboxminted{firstline=60,lastline=64}{examples/ttl.py}
+
+\subsection{Edge counting in a 1ms window}
+The \texttt{TTLInOut} class implements \texttt{gate\char`_rising()}, \texttt{gate\char`_falling()} \& \texttt{gate\char`_both()} for rising edge, falling edge, both rising edge \& falling edge detection respectively.
+The channel should be configured as input in both gateware and hardware. Invoke one of the 3 methods to start edge detection.
+\inputcolorboxminted{firstline=14,lastline=15}{examples/ttl_in.py}
+Input signal can generated from another TTL channel or from other sources. Manipulate the timeline cursor to generate TTL pulses using the same kernel.
+\inputcolorboxminted{firstline=10,lastline=22}{examples/ttl_in.py}
+The detected edges are registered to the RTIO input FIFO. By default, the FIFO can hold 64 events. The FIFO depth is defined by the \texttt{ififo\char`_depth} parameter for \texttt{Channel} class in \texttt{rtio/channel.py}.
+Once the threshold is exceeded, an \texttt{RTIOOverflow} exception will be triggered when the input events are read by the kernel CPU.
+Finally, invoke \texttt{count()} to retrieve the edge count from the input gate.
+
+The RTIO system can report at most one edge detection event for every coarse RTIO cycle. In principle, to guarantee all rising edges are counted (with \texttt{gate\char`_rising()} invoked), the theoretical minimum separation between rising edges is one coarse RTIO cycle (typically 8 ns). However, both the electrical specifications and the possibility of triggering \texttt{RTIOOverflow} exceptions should also be considered.
+
+\newpage
+\subsection{Edge counting using \texttt{EdgeCounter}}
+This example code uses a gateware counter to substitute the software counter, which has a maximum count rate of approximately 1 million events per second. If a gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
+\inputcolorboxminted{firstline=31,lastline=36}{examples/ttl_in.py}
+Edges are detected by comparing the current input state and that of the previous coarse RTIO cycle. Therefore, the theoretical minimum separation between 2 opposite edges is 1 coarse RTIO cycle (typically 8 ns).
+
+\subsection{Responding to an external trigger}
+One channel needs to be configured as input, and the other as output.
+\inputcolorboxminted{firstline=45,lastline=51}{examples/ttl_in.py}
+
+\subsection{62.5 MHz clock signal generation}
+A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal. Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle. Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2.
+
+Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
+
+\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
+
+\newpage
+\subsection{Minimum sustained event separation}
+The minimum sustained event separation is the least time separation between input gated events for which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions. The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
+
+\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
+
+\begin{center}
+\begin{table}[H]
+    \captionof{table}{Minimum sustained event separation of different carriers}
+    \centering
+    \begin{tabular}{|c|c|c|}
+    \hline
+    Carrier  & Kasli v1.1 & Kasli-SoC \\ \hline
+    Duration & 650 ns     & 600 ns    \\ \hline
+    \end{tabular}
+    \end{table}
+\end{center}
+
+\ordersection{2118 BNC-TTL/2128 SMA-TTL}
+
+\finalfootnote
+
+\end{document}

2128.tex

@@ -1,473 +0,0 @@
-\documentclass[10pt]{datasheet}
-\usepackage{palatino}
-\usepackage{textgreek}
-\usepackage{minted}
-\usepackage{tcolorbox}
-\usepackage{etoolbox}
-\BeforeBeginEnvironment{minted}{\begin{tcolorbox}[colback=white]}%
-\AfterEndEnvironment{minted}{\end{tcolorbox}}%
-
-\usepackage[justification=centering]{caption}
-
-\usepackage[utf8]{inputenc}
-\usepackage[english]{babel}
-\usepackage[english]{isodate}
-
-\usepackage{graphicx}
-\usepackage{subfigure}
-
-\usepackage{tikz}
-\usepackage{pgfplots}
-\usepackage{circuitikz}
-\usetikzlibrary{calc}
-\usetikzlibrary{fit,backgrounds} 
-
-\title{2128 SMA-TTL}
-\author{M-Labs Limited}
-\date{July 2021}
-\revision{Revision 1}
-\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
-
-\begin{document}
-\maketitle
-
-\section{Features}
-
-\begin{itemize}
-\item{8 channels.}
-\item{Input and output capable.}
-\item{Galvanically isolated.}
-\item{3ns minimum pulse width.}
-\item{SMA connectors.}
-\end{itemize}
-
-\section{Applications}
-
-\begin{itemize}
-\item{Photon counting.}
-\item{External equipment trigger.}
-\item{Optical shutter control.}
-\end{itemize}
-
-\section{General Description}
-The 2128 SMA-TTL card is a 4hp EEM module part of the ARTIQ Sinara family.
-It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
-
-It provides two banks of four digital channels each, with SMA connectors.
-Each bank has individual ground isolation.
-The direction (input or output) of each bank can be selected using DIP switches.
-Each channel supports 50\textOmega~terminations individually controllable using DIP switches.
-Outputs tolerate short circuits indefinitely.
-The card support a minimum pulse width of 3ns.
-
-
-% Switch to next column
-\vfill\break
-
-\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
-\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
-
-\begin{figure}[h]
-    \centering
-    \scalebox{0.88}{
-    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
-
-        \begin{scope}[yshift=1.3cm]
-
-            \draw[color=white, text=black] (-0.1,0) node[twoportshape,t={SMA 0}, circuitikz/bipoles/twoport/width=1.2, scale=0.4] (sma0) {};
-            \draw[color=white, text=black] (-0.1,-0.7) node[twoportshape,t={SMA 1}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma1) {};
-            \draw[color=white, text=black] (-0.1,-1.4) node[twoportshape,t={SMA 2}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma2) {};        
-            \draw[color=white, text=black] (-0.1,-2.1) node[twoportshape,t={SMA 3}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma3) {};
-
-            \node [label={[xshift=-0.18cm, yshift=-0.305cm]\tiny{SMA 0}}] {};
-            \node [label={[xshift=-0.18cm, yshift=-0.97cm]\tiny{SMA 1}}] {};
-            \node [label={[xshift=-0.18cm, yshift=-1.64cm]\tiny{SMA 2}}] {};
-            \node [label={[xshift=-0.18cm, yshift=-2.302cm]\tiny{SMA 3}}] {};
-
-            % draw female SMA_0,1,2,3 
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}                        
-
-
-
-            \draw (1.6,-1.05) node[twoportshape,t={Octal Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus1) {};
-
-            \draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso1) {};
-            \draw (3.05,-0.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso2) {};
-            \draw (3.05,-1.4) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso3) {};
-            \draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso4) {};
-            \draw (3.05,-2.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso1) {};
-
-            \draw (4.5,-1.15) node[twoportshape,t=\MymyLabel{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds1) {};
-
-            \draw (6.8,-0.9) -- ++(0.00001,0) node[twoportshape, anchor=left, t={EEM port}, circuitikz/bipoles/twoport/width=6, scale=0.6, rotate=-90] (kasli) {} ;
-            \draw (0.8,-3.5) node[twoportshape,t=\MymyLabel{Per-bank \phantom{spac} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
-            \draw (3.05,-3.5) node[twoportshape,t=\MymyLabel{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
-
-            \draw (5.68,-2.3) node[twoportshape,t=EEPROM, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom) {};
-
-            \draw (0.8,-2.7) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
-
-            % Termination Switch 1,2,3,4
-            \begin{scope}[xshift=0.9cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-                \draw (0.4,0) to[short,-o](0.75,0);
-                \draw (0.78,0)-- +(30:0.46);
-                \draw (1.25,0)to[short,o-](1.6,0)   ;   
-            \end{scope}
-            \begin{scope}[xshift=1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-                \draw (0.4,0) to[short,-o](0.75,0);
-                \draw (0.78,0)-- +(30:0.46);
-                \draw (1.25,0)to[short,o-](1.6,0)   ;   
-            \end{scope}
-            \begin{scope}[xshift=1.1cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-                \draw (0.4,0) to[short,-o](0.75,0);
-                \draw (0.78,0)-- +(30:0.46);
-                \draw (1.25,0)to[short,o-](1.6,0)   ;   
-            \end{scope}
-            \begin{scope}[xshift=1.2cm, yshift=-2.66cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-                \draw (0.4,0) to[short,-o](0.75,0);
-                \draw (0.78,0)-- +(30:0.46);
-                \draw (1.25,0)to[short,o-](1.6,0)   ;   
-            \end{scope}
-
-        \end{scope}
-
-        % I/O Switch 1, 2
-        \begin{scope}[xshift=1.2cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-            \draw (0.4,0) to[short,-o](0.75,0);
-            \draw (0.78,0)-- +(30:0.46);
-            \draw (1.25,0)to[short,o-](1.6,0)   ;   
-        \end{scope}
-        \begin{scope}[xshift=1.32cm, yshift=-1.98cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-            \draw (0.4,0) to[short,-o](0.75,0);
-            \draw (0.78,0)-- +(30:0.46);
-            \draw (1.25,0)to[short,o-](1.6,0)   ;   
-        \end{scope}
-
-        \draw (0.8,-3.05) node[twoportshape,t=\MymyLabel{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
-
-        % Termination Switch 5,6,7,8
-        \begin{scope}[xshift=0.9cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-            \draw (0.4,0) to[short,-o](0.75,0);
-            \draw (0.78,0)-- +(30:0.46);
-            \draw (1.25,0)to[short,o-](1.6,0)   ;   
-        \end{scope}
-        \begin{scope}[xshift=1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-            \draw (0.4,0) to[short,-o](0.75,0);
-            \draw (0.78,0)-- +(30:0.46);
-            \draw (1.25,0)to[short,o-](1.6,0)   ;   
-        \end{scope}
-        \begin{scope}[xshift=1.1cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-            \draw (0.4,0) to[short,-o](0.75,0);
-            \draw (0.78,0)-- +(30:0.46);
-            \draw (1.25,0)to[short,o-](1.6,0)   ;   
-        \end{scope}
-        \begin{scope}[xshift=1.2cm, yshift=-3.02cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
-            \draw (0.4,0) to[short,-o](0.75,0);
-            \draw (0.78,0)-- +(30:0.46);
-            \draw (1.25,0)to[short,o-](1.6,0)   ;   
-        \end{scope}
-
-        % channel 5,6,7,8
-        \begin{scope}[yshift=-3.6cm]
-            \draw[color=white, text=black]  (-0.1,0) node[twoportshape,t={SMA 4}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma4) {};
-            \draw[color=white, text=black]  (-0.1,-0.7) node[twoportshape,t={SMA 5}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma5) {};        
-            \draw[color=white, text=black]  (-0.1,-1.4) node[twoportshape,t={SMA 6}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma6) {};
-            \draw[color=white, text=black]  (-0.1,-2.1) node[twoportshape,t={SMA 7}, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma7) {};
-
-            \node [label={[xshift=-0.18cm, yshift=-0.305cm]\tiny{SMA 4}}] {};
-            \node [label={[xshift=-0.18cm, yshift=-0.97cm]\tiny{SMA 5}}] {};
-            \node [label={[xshift=-0.18cm, yshift=-1.64cm]\tiny{SMA 6}}] {};
-            \node [label={[xshift=-0.18cm, yshift=-2.302cm]\tiny{SMA 7}}] {};
-
-            % draw female SMA 4,5,6,7
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}
-            \begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
-                \draw (0,0.65) -- (0,3);
-                \clip (-1.5,0) rectangle (1.5,1.5);
-                \draw (0,0) circle(1.5);
-                \clip (-0.8,0) rectangle (0.8,0.8);
-                \draw (0,0) circle(0.8);
-            \end{scope}    
-
-
-            \draw (1.6,-1.05) node[twoportshape,t={Octal Bus Transceiver}, circuitikz/bipoles/twoport/width=2.5, scale=0.7, rotate=-90 ] (bus2) {};
-
-            \draw (3.05,-0) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso5) {};
-            \draw (3.05,-0.7) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso6) {};
-            \draw (3.05,-1.4) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso7) {};
-            \draw (3.05,-2.1) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (iso8) {};
-            \draw (3.05,0.6) node[twoportshape,t={Isolator}, circuitikz/bipoles/twoport/width=1.3, scale=0.4] (i2ciso2) {};
-
-            \draw (4.5,-1.05) node[twoportshape,t=\MymyLabel{4-Channel LVDS}{Line Transceiver}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (lvds2) {};
-
-        \end{scope}
-
-        % Drawing Connections
-        \draw [latexslim-latexslim] (sma0.east) -- ++(1,0);
-        \draw [latexslim-latexslim] (sma1.east) -- ++(1,0);
-        \draw [latexslim-latexslim] (sma2.east) -- ++(1,0);
-        \draw [latexslim-latexslim] (sma3.east) -- ++(1,0);
-        \draw [latexslim-latexslim] (sma4.east) -- ++(1,0);
-        \draw [latexslim-latexslim] (sma5.east) -- ++(1,0);
-        \draw [latexslim-latexslim] (sma6.east) -- ++(1,0);
-        \draw [latexslim-latexslim] (sma7.east) -- ++(1,0);
-
-        \draw [latexslim-latexslim] (iso1.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso2.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso3.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso4.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso1.east) -- ++(0.69,0);
-        \draw [latexslim-latexslim] (iso2.east) -- ++(0.69,0);
-        \draw [latexslim-latexslim] (iso3.east) -- ++(0.69,0);
-        \draw [latexslim-latexslim] (iso4.east) -- ++(0.69,0);
-
-        \draw [latexslim-latexslim] (iso5.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso6.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso7.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso8.west) -- ++(-0.72,0) ;
-        \draw [latexslim-latexslim] (iso5.east) -- ++(0.7,0);
-        \draw [latexslim-latexslim] (iso6.east) -- ++(0.7,0);
-        \draw [latexslim-latexslim] (iso7.east) -- ++(0.7,0);
-        \draw [latexslim-latexslim] (iso8.east) -- ++(0.7,0);
-
-        \draw [latexslim-] (eeprom.south) -- ++(0,-0.95);
-
-        \draw [latexslim-latexslim] (lvds1.north) -- ++(1.61,0);
-        \draw [latexslim-latexslim] (lvds2.north) -- ++(1.62,0);
-        \draw [latexslim-latexslim] (i2c.east) -- ++(2.77,0);
-        \draw [latexslim-] (i2c.west) -- (ioswitch.east) ;
-
-        \draw [-latexslim] (i2c.north east) -- (lvds1.south east);
-        \draw [-latexslim] (i2c.south east) -- (lvds2.south west);
-
-        \draw [-latexslim] (i2ciso1.west) -- (bus1.north east);
-        \draw [thin] [-latexslim] (i2c.north) -- (i2ciso1.south);
-
-        \draw [-latexslim] (i2ciso2.west) -- (bus2.north west);
-        \draw [thin] [-latexslim] (i2c.south) -- (i2ciso2.north);
-
-
-        % termination switch connection
-        \draw (0.65,-1.18) -- ++(0,2.47) ;
-        \draw (0.75,-1.18) -- ++(0,1.77) ;
-        \draw (0.85,-1.18) -- ++(0,1.07) ;
-        \draw (0.95,-1.18) -- ++(0,0.37) ;
-
-        \draw (0.65,-3.25) -- ++(0,-2.45) ;
-        \draw (0.75,-3.25) -- ++(0,-1.75) ;
-        \draw (0.85,-3.25) -- ++(0,-1.05) ;
-        \draw (0.95,-3.25) -- ++(0,-0.35) ;
-
-        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(sma0) (i2ciso1.south west)] (box1) {};
-        \node[fill=white, rotate=-90] at (box1.west) {GND BANK 1};
-        \node[fill=white,above] at (box1.north) {\tiny{Either all 4 channels are inputs or all 4 channels are outputs }};
-
-
-        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(sma4)(termswitch2) (iso8.south west)] (box2) {};
-        \node[fill=white, rotate=-90] at (box2.west) {GND BANK 2};
-        \node[fill=white,below] at (box2.south) {\tiny{Either all 4 channels are inputs or all 4 channels are outputs }};
-
-    \end{circuitikz}
-    }
-
-    \caption{Simplified Block Diagram}
-\end{figure}
-
-\begin{figure}[h]
-    \centering
-    \includegraphics[width=1.18in]{photo2128.jpg}
-    \caption{SMA-TTL Card photo}
-\end{figure}
-
-% For wide tables, a single column layout is better. It can be switched
-% page-by-page.
-\onecolumn
-
-\section{Electrical Specifications}
-All specifications are in $0\degree C \leq T_A \leq 70\degree C$ unless otherwise noted.
-
-\begin{table}[h]
-\begin{threeparttable}
-\caption{Recommended Operating Conditions}
-\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
-    \thickhline
-    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
-    \textbf{Unit} & \textbf{Conditions} \\
-    \hline
-    High-level input voltage & $V_{IH}$ & 2 &  &  & V &  \\
-    \hline
-    Low-level input voltage & $V_{IL}$ & & & 0.8 & V & \\
-    \hline
-    Input clamp current & $I_{OH}$ & & & -18 & mA & termination disabled \\
-    \hline
-    High-level output current & $I_{OH}$ & & & -160 & mA & \\
-    \hline
-    Low-level output current & $I_{OL}$ & & & 376 & mA & \\
-    \thickhline
-\end{tabularx}
-\end{threeparttable}
-\end{table}
-
-\begin{table}[h]
-\begin{threeparttable}
-\caption{Electrical Characteristics}
-\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
-    \thickhline
-    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
-    \textbf{Unit} & \textbf{Conditions} \\
-    \hline
-    High-level output voltage & $V_{OH}$ & 2 &  &  & V & $I_{OH}$=-160mA \\
-     &  & 2.7 &  &  & V & $I_{OH}$=-6mA \\
-    \hline
-    Low-level output voltage & $V_{OL}$ & & 0.42 & 0.55 & V & $I_{OL}$=188mA \\
-    &  &  &  & 0.7 & V & $I_{OL}$=376mA \\
-    \hline
-    Pulse width distortion & $PWD$ & & 0.2 & 4.5 & ns &  \\
-    \hline
-    Peak jitter & $T_{JIT(PK)}$ & & 350 & & ps &  \\
-    \thickhline
-\end{tabularx}
-\end{threeparttable}
-\end{table}
-
-\section{Example ARTIQ code}
-The sections below demonstrate simple usage scenarios of the 2128 SMA-TTL card with the ARTIQ control system.
-They do not exhaustively demonstrate all the features of the ARTIQ system.
-The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
-
-Timing accuracy in the examples below is well under 1 nanosecond thanks to the ARTIQ RTIO system.
-
-\subsection{One pulse per second}
-The channel should be configured as output in both the gateware and hardware.
-
-\begin{minted}{python}
-@kernel
-def run(self):
-    self.core.reset()
-    while True:
-        self.ttl0.pulse(500*ms)
-        delay(500*ms)
-\end{minted}
-
-\newpage
-
-\subsection{Morse code}
-This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
-\begin{minted}{python}
-def prepare(self):
-    # As of ARTIQ-6, the ARTIQ compiler has limited string handling
-    # capabilities, so we pass a list of integers instead.
-    message = ".- .-. - .. --.-"
-    self.commands = [{".": 1, "-": 2, " ": 3}[c] for c in message]
-
-@kernel
-def run(self):
-    self.core.reset()
-    for cmd in self.commands:
-        if cmd == 1:
-            self.led.pulse(100*ms)
-            delay(100*ms)
-        if cmd == 2:
-            self.led.pulse(300*ms)
-            delay(100*ms)
-        if cmd == 3:
-            delay(700*ms)
-\end{minted}
-
-\subsection{Counting rising edges in a 1ms window}
-The channel should be configured as input in both the gateware and hardware.
-
-\begin{minted}{python}
-@kernel
-def run(self):
-    self.core.reset()
-    gate_end_mu = self.ttl0.gate_rising(1*ms)
-    counts = self.ttl0.count()
-    print(counts)
-\end{minted}
-
-This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
-If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
-\begin{minted}{python}
-@kernel
-def run(self):
-    self.core.reset()
-    self.edgecounter0.gate_rising(1*ms)
-    counts = self.edgecounter0.fetch_count()
-    print(counts)
-\end{minted}
-
-\newpage 
-
-\subsection{Responding to an external trigger}
-One channel needs to be configured as input, and the other as output.
-
-\begin{minted}{python}
-@kernel
-def run(self):
-    self.core.reset()
-    self.ttlin.gate_rising(5*ms)
-    timestamp_mu = self.ttlin.timestamp_mu()
-    at_mu(timestamp_mu + self.core.seconds_to_mu(10*ms))
-    self.ttlout.pulse(1*us)
-\end{minted}
-
-\section{Ordering Information}
-To order, please visit \url{https://m-labs.hk} and select the 2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
-
-\section*{}
-\vspace*{\fill}
-
-\begin{footnotesize}
-Information furnished by M-Labs Limited is believed to be accurate and reliable. However, no responsibility is assumed by M-Labs Limited for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
-Specifications subject to change without notice.
-\end{footnotesize}
-
-\end{document}

2238.tex

@@ -0,0 +1,557 @@
+\input{preamble.tex}
+\graphicspath{{images/2238}{images}}
+
+\title{2238 MCX-TTL}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 2}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{16 MCX-TTL channels}
+\item{Input and output capable}
+\item{No galvanic isolation}
+\item{High speed and low jitter}
+\item{MCX connectors}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Photon counting}
+\item{External equipment trigger}
+\item{Optical shutter control}
+\end{itemize}
+
+\section{General Description}
+
+The 2238 MCX-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+Each card provides four banks of four digital channels each for a total of sixteen digital channels, with MCX connectors in the front panel, controlled through two EEM connectors. Each individual EEM connector controls two banks independently. Single EEM operation is possible. The direction (input or output) of each bank can be selected using DIP switches, and applies to all four channels of the bank.
+
+Each channel supports 50\textOmega~terminations individually controllable using DIP switches. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.88}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+        % Node to pin-point the locations of MCX symbols
+        \draw[color=white, text=black] (-0.1, 0.7) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx0) {};
+        \draw[color=white, text=black] (-0.1, 0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx1) {};
+        \draw[color=white, text=black] (-0.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx2) {};
+        \draw[color=white, text=black] (-0.1, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx3) {};
+        \draw[color=white, text=black] (-0.1, -1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx4) {};
+        \draw[color=white, text=black] (-0.1, -1.4) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx5) {};
+        \draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx6) {};
+        \draw[color=white, text=black] (-0.1, -2.1) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx7) {};
+        \draw[color=white, text=black] (-0.1, -4.2) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx8) {};
+        \draw[color=white, text=black] (-0.1, -4.55) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx9) {};
+        \draw[color=white, text=black] (-0.1, -4.9) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx10) {};
+        \draw[color=white, text=black] (-0.1, -5.25) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx11) {};
+        \draw[color=white, text=black] (-0.1, -5.95) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx12) {};
+        \draw[color=white, text=black] (-0.1, -6.3) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx13) {};
+        \draw[color=white, text=black] (-0.1, -6.65) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx14) {};
+        \draw[color=white, text=black] (-0.1, -7) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mcx15) {};
+
+        % Labels for IO 0-15
+        \node [label=left:\tiny{IO 0}] at (0.35, 0.7) {};
+        \node [label=left:\tiny{IO 1}] at (0.35, 0.35) {};
+        \node [label=left:\tiny{IO 2}] at (0.35, 0) {};
+        \node [label=left:\tiny{IO 3}] at (0.35, -0.35) {};
+        \node [label=left:\tiny{IO 4}] at (0.35, -1.05) {};
+        \node [label=left:\tiny{IO 5}] at (0.35, -1.4) {};
+        \node [label=left:\tiny{IO 6}] at (0.35, -1.75) {};
+        \node [label=left:\tiny{IO 7}] at (0.35, -2.1) {};
+        \node [label=left:\tiny{IO 8}] at (0.35, -4.2) {};
+        \node [label=left:\tiny{IO 9}] at (0.35, -4.55) {};
+        \node [label=left:\tiny{IO 10}] at (0.35, -4.9) {};
+        \node [label=left:\tiny{IO 11}] at (0.35, -5.25) {};
+        \node [label=left:\tiny{IO 12}] at (0.35, -5.95) {};
+        \node [label=left:\tiny{IO 13}] at (0.35, -6.3) {};
+        \node [label=left:\tiny{IO 14}] at (0.35, -6.65) {};
+        \node [label=left:\tiny{IO 15}] at (0.35, -7) {};
+
+        % Draw all female MCX connectors
+        % Bank 1
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=-10cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=-5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+
+        % Bank 2
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=15cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+
+        % Bank 3
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=60cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=65cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=70cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=75cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+
+        % Bank 4
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=85cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=90cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=95cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=100cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+
+        % Draw bank boundaries
+        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.2em, fit=(mcx0)(mcx3)] (bank0) {};
+        \node[fill=white, scale=0.7, rotate=-90] at (bank0.west) {Bank 0};
+        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.2em, fit=(mcx4)(mcx7)] (bank1) {};
+        \node[fill=white, scale=0.7, rotate=-90] at (bank1.west) {Bank 1};
+        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.2em, fit=(mcx8)(mcx11)] (bank2) {};
+        \node[fill=white, scale=0.7, rotate=-90] at (bank2.west) {Bank 2};
+        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.2em, fit=(mcx12)(mcx15)] (bank3) {};
+        \node[fill=white, scale=0.7, rotate=-90] at (bank3.west) {Bank 3};
+
+        % Draw bus transceivers
+        \draw (3.25, -0.7) node[twoportshape,t=\fourcm{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus0) {};
+        \draw (3.25, -5.6) node[twoportshape,t=\fourcm{IO Bus}{Transceivers}, circuitikz/bipoles/twoport/width=3.2, scale=0.7, rotate=-90 ] (bus1) {};
+
+        % Draw termination switches
+        % Bus transceiver 0
+        \draw (1.7, 1.2) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch0) {};
+        \begin{scope}[xshift=1.8cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.9cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=2.0cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=2.1cm, yshift=1.23cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+
+        % Bus transceiver 1
+        \draw (1.5, -2.6) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch1) {};
+        \begin{scope}[xshift=1.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.7cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.8cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.9cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+
+        % Bus transceiver 2
+        \draw (1.7, -3.7) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch2) {};
+        \begin{scope}[xshift=1.8cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.9cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=2cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=2.1cm, yshift=-3.67cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+
+        % Bus transceiver 3
+        \draw (1.5, -7.5) node[twoportshape,t=\fourcm{High-Z/50\textOmega}{Switch \phantom{ssssss} }, circuitikz/bipoles/twoport/width=2, scale=0.4] (termswitch3) {};
+        \begin{scope}[xshift=1.6cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.7cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.8cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=1.9cm, yshift=-7.47cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+
+        % Connection termination switches to each IO line
+        % IO 0, 2, 4, 6
+        \draw [-] (1.4, 1) -- (1.4, 0.7);
+        \draw [-] (1.6, 1) -- (1.6, 0);
+        \draw [-] (1.8, 1) -- (1.8, -1.05);
+        \draw [-] (2, 1) -- (2, -1.75);
+
+        % IO 1, 3, 5, 7
+        \draw [-] (1.2, -2.4) -- (1.2, 0.35);
+        \draw [-] (1.4, -2.4) -- (1.4, -0.35);
+        \draw [-] (1.6, -2.4) -- (1.6, -1.4);
+        \draw [-] (1.8, -2.4) -- (1.8, -2.1);
+
+        % IO 8, 10, 12, 14
+        \draw [-] (1.4, -3.9) -- (1.4, -4.2);
+        \draw [-] (1.6, -3.9) -- (1.6, -4.9);
+        \draw [-] (1.8, -3.9) -- (1.8, -5.95);
+        \draw [-] (2, -3.9) -- (2, -6.65);
+
+        % IO 9, 11, 13, 15
+        \draw [-] (1.2, -7.3) -- (1.2, -4.55);
+        \draw [-] (1.4, -7.3) -- (1.4, -5.25);
+        \draw [-] (1.6, -7.3) -- (1.6, -6.3);
+        \draw [-] (1.8, -7.3) -- (1.8, -7);
+
+        % Connect I/Os to corresponding tranceivers
+        \draw [latexslim-latexslim] (mcx0) -- (2.9, 0.7);
+        \draw [latexslim-latexslim] (mcx1) -- (2.9, 0.35);
+        \draw [latexslim-latexslim] (mcx2) -- (2.9, 0);
+        \draw [latexslim-latexslim] (mcx3) -- (2.9, -0.35);
+
+        \draw [latexslim-latexslim] (mcx4) -- (2.9, -1.05);
+        \draw [latexslim-latexslim] (mcx5) -- (2.9, -1.4);
+        \draw [latexslim-latexslim] (mcx6) -- (2.9, -1.75);
+        \draw [latexslim-latexslim] (mcx7) -- (2.9, -2.1);
+
+        \draw [latexslim-latexslim] (mcx8) -- (2.9, -4.2);
+        \draw [latexslim-latexslim] (mcx9) -- (2.9, -4.55);
+        \draw [latexslim-latexslim] (mcx10) -- (2.9, -4.9);
+        \draw [latexslim-latexslim] (mcx11) -- (2.9, -5.25);
+
+        \draw [latexslim-latexslim] (mcx12) -- (2.9, -5.95);
+        \draw [latexslim-latexslim] (mcx13) -- (2.9, -6.3);
+        \draw [latexslim-latexslim] (mcx14) -- (2.9, -6.65);
+        \draw [latexslim-latexslim] (mcx15) -- (2.9, -7);
+
+        % Draw LVDS transceivers
+        \draw (5.05, -0.025) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds0) {};
+        \draw (5.05, -1.675) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds1) {};
+        \draw (5.05, -4.625) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds2) {};
+        \draw (5.05, -6.275) node[twoportshape,t={\fourcm{LVDS}{Transceiver}}, circuitikz/bipoles/twoport/width=2, scale=0.5, rotate=-90 ] (lvds3) {};
+
+        % Aesthetic EEPROM at each end of LVDS transceivers
+        \draw (5.05, 1.1) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom0) {};
+        \draw (5.05, -7.4) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (eeprom1) {};
+
+        % I/O expander
+        \draw (6.65, -3.5) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
+
+        % I/O direction switches
+        \draw (5.05, -2.8) node[twoportshape,t=\fourcm{Per-bank \phantom{space} }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.44] (ioswitch) {};
+        \begin{scope}[xshift=5.3cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=5.4cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=5.5cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+        \begin{scope}[xshift=5.6cm, yshift=-2.57cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0);
+        \end{scope}
+
+        % EEM Ports
+        \draw (6.65, -0.5) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem0) {};
+        \draw (6.65, -5.8) node[twoportshape, t={EEM Port 1}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem1) {};
+
+        % Connect I/O expander & direction switches to bus transceivers block
+        % The transceivers had been grouped up, there is no need to label I/O direction indices anymore
+        % It might still be useful to identify the direction line itself, though
+        \draw [latexslim-] (i2c.west) -- (3.25, -3.5);
+        \draw [-] (ioswitch.south) -- (5.05, -3.5);
+        \draw [latexslim-latexslim] (bus0.east) -- (bus1.west);
+        \node [label=center:\tiny{IO Direction}] at (4.1, -3.4) {};
+
+        % Connect LVDS transceivers to bus transceivers, with labelling
+        \draw [latexslim-latexslim] (lvds0.south) -- (3.6, -0.025);
+        \node [label=center:\tiny{EEM}] at (4.2, 0.075) {};
+        \node [label=center:\tiny{0..3}] at (4.2, -0.125) {};
+        \draw [latexslim-latexslim] (lvds1.south) -- (3.6, -1.675);
+        \node [label=center:\tiny{EEM}] at (4.2, -1.575) {};
+        \node [label=center:\tiny{4..7}] at (4.2, -1.775) {};
+        \draw [latexslim-latexslim] (lvds2.south) -- (3.6, -4.625);
+        \node [label=center:\tiny{EEM}] at (4.2, -4.525) {};
+        \node [label=center:\tiny{8..11}] at (4.2, -4.725) {};
+        \draw [latexslim-latexslim] (lvds3.south) -- (3.6, -6.275);
+        \node [label=center:\tiny{EEM}] at (4.2, -6.175) {};
+        \node [label=center:\tiny{12..15}] at (4.2, -6.375) {};
+
+        % Connect EEM0 & EEM1
+        \draw [latexslim-latexslim] (lvds0.north) -- (6.3, -0.025);
+        \draw [latexslim-latexslim] (lvds1.north) -- (6.3, -1.675);
+        \draw [latexslim-latexslim] (lvds2.north) -- (6.3, -4.625);
+        \draw [latexslim-latexslim] (lvds3.north) -- (6.3, -6.275);
+        \draw [latexslim-latexslim] (eeprom0.east) -- (6.3, 1.1);
+        \draw [latexslim-latexslim] (eeprom1.east) -- (6.3, -7.4);
+        \draw [latexslim-latexslim] (eem0.east) -- (i2c.north);
+
+        % Reminder: IO directions are only selectable by bank. Channels from the same bank must have the same IO direction.
+        % Might be unnecessary as I/O directions signals are labelled with the "Bank" prefix.
+        \node [label={center:\tiny{Channels from the same bank}}] at (1.4, -3.05) {};
+        \node [label={center:\tiny{must have the same IO direction.}}] at (1.4, -3.25) {};
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2in]{photo2238.jpg}
+    \caption{MCX-TTL card}
+    \includegraphics[angle=90, height=0.6in]{DIO_MCX_FP.pdf}
+    \caption{MCX-TTL front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{2238 MCX-TTL}{https://github.com/sinara-hw/DIO_MCX/wiki}
+
+\section{Electrical Specifications}
+
+All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the bus transceiver IC (74LVT162245MTD\footnote{\label{transceiver}\url{https://www.onsemi.com/pdf/datasheet/74lvt162245-d.pdf}}).
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Recommended Operating Conditions}
+\begin{tabularx}{\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Input voltage & 0 & & 5.5* & V \\
+    \hline
+    High-level output current & & & -24 & mA \\
+    \hline
+    Low-level output current & & & 24 & mA \\
+    \hline
+    Input edge rate & & & 10 & ns/V & $0.8V \leq V_I \leq 2.0V$ \\
+    \thickhline
+    \multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage should not exceed 5V.}
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Electrical Characteristics}
+\begin{tabularx}{\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Input clamp diode voltage & & & -1.2 & V & $I_I =-36 mA$ \\
+    \hline
+    Input high voltage & 2.0 & & & V & \\
+    \hline
+    Input low voltage & & & 0.8 & V & \\
+    \hline
+    Output high voltage & 2.0 & & & V & $I_{OH}=-24mA$ \\
+    & 3.1 & & & V & $I_{OH}=-200\mu A$ \\
+    \hline
+    Output low voltage & & & 0.8 & V & $I_{OL}=-24mA$ \\
+    & & & 0.2 & V & $I_{OL}=-200\mu A$ \\
+    \hline
+    Input current & & & 20 & \textmu A & $V_I=5.5V$ \\
+    & & & 2 & \textmu A & $V_I=3.3V$ \\
+    & & & -10 & \textmu A & $V_I=0V$ \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+\section{Configuring IO Direction \& Termination}
+IO direction and termination must be configured by switches. The termination switches are found at the top and the IO direction switches at the middle of the card respectively.
+\begin{multicols}{2}
+Termination switches between high impedence (OFF) and 50\textOmega~(ON). Note that termination switches are by-channel but IO direction switches are by-bank.
+
+\begin{itemize}
+    \itemsep0em
+    \item IO direction switch closed (\texttt{ON}) \\
+          Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
+    \item IO direction switch open (OFF) \\
+          The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
+\end{itemize}
+\columnbreak
+\begin{center}
+    \centering
+    \includegraphics[height=1.7in]{mcx_ttl_switches.jpg}
+    \captionof{figure}{Position of switches}
+\end{center}
+\end{multicols}
+
+\newpage
+\codesection{2238 MCX-TTL card}
+
+Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
+
+\subsection{One pulse per second}
+The channel should be configured as output in both the gateware and hardware.
+\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
+
+\subsection{Morse code}
+This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
+\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
+
+\newpage
+\subsection{Edge counting in an 1ms window}
+The channel should be configured as input in both gateware and hardware.
+\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
+
+This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
+If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
+\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
+
+\subsection{Responding to an external trigger}
+One channel needs to be configured as input, and the other as output.
+\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
+
+\ordersection{2238 MCX-TTL}
+
+\finalfootnote
+
+\end{document}

2245.tex

@@ -0,0 +1,627 @@
+\input{preamble.tex}
+\graphicspath{{images/2245}{images}}
+
+\usepackage{tikz-timing}
+\usetikztiminglibrary{counters}
+
+\title{2245 LVDS-TTL}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 2}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{16 LVDS-TTL channels.}
+\item{Input- and output-capable}
+\item{No galvanic isolation}
+\item{High speed and low jitter}
+\item{RJ45 connectors}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Photon counting}
+\item{External equipment trigger}
+\item{Optical shutter control}
+\item{Serial communication with remote devices}
+\end{itemize}
+
+\section{General Description}
+The 2245 LVDS-TTL card is a 4hp EEM module. It adds general-purpose digital I/O capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+Each card provides sixteen total digital channels, with four RJ45 connectors in the front panel, controlled through 2 EEM connectors. Each RJ45 connector exposes four LVDS digital channels. Each individual EEM connector controls eight channels independently. Single EEM operation is possible. The direction (input or output) of each channel can be selected individually using DIP switches.
+
+Outputs are intended to drive 100\textOmega~loads and inputs are 100\textOmega~terminated. This card can achieve higher speed and lower jitter than the isolated 2118/2128 BNC/SMA-TTL cards. Only shielded Ethernet Cat-6 cables should be connected.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.88}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        % RJ45 Connectors
+        \draw (0, 2.8) node[twoportshape, t={\twocm{RJ45}{CH 0-3}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth0) {};
+        \draw (0, 1.0) node[twoportshape, t={\twocm{RJ45}{CH 4-7}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth1) {};
+        \draw (0, -1.0) node[twoportshape, t={\twocm{RJ45}{CH 8-11}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth2) {};
+        \draw (0, -2.8) node[twoportshape, t={\twocm{RJ45}{CH 12-15}}, circuitikz/bipoles/twoport/width=1.4, scale=0.5, rotate=-90] (eth3) {};
+
+        % Repeaters for channels
+
+        % Channel 7 repeaters
+        \draw (1.8, 0.4) node[twoportshape, t={\twocm{CH 7}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep7) {};
+
+        % Omission dots
+        \node at (1.8, 0.8)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, 1.0)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, 1.2)[circle,fill,inner sep=0.7pt]{};
+
+        % Channel 4 repeaters
+        \draw (1.8, 1.6) node[twoportshape, t={\twocm{CH 4}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep4) {};
+
+        % Channel 3 repeaters
+        \draw (1.8, 2.2) node[twoportshape, t={\twocm{CH 3}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep3) {};
+
+        % Omission dots
+        \node at (1.8, 2.6)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, 2.8)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, 3.0)[circle,fill,inner sep=0.7pt]{};
+
+        % Channel 0 repeaters
+        \draw (1.8, 3.4) node[twoportshape, t={\twocm{CH 0}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep0) {};
+
+        % Channel 8 repeaters
+        \draw (1.8, -0.4) node[twoportshape, t={\twocm{CH 8}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep8) {};
+
+        % Omission dots
+        \node at (1.8, -0.8)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, -1.0)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, -1.2)[circle,fill,inner sep=0.7pt]{};
+
+        % Channel 11 repeaters
+        \draw (1.8, -1.6) node[twoportshape, t={\twocm{CH 11}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep11) {};
+
+        % Channel 12 repeaters
+        \draw (1.8, -2.2) node[twoportshape, t={\twocm{CH 12}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep12) {};
+
+        % Omission dots
+        \node at (1.8, -2.6)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, -2.8)[circle,fill,inner sep=0.7pt]{};
+        \node at (1.8, -3.0)[circle,fill,inner sep=0.7pt]{};
+
+        % Channel 15 repeaters
+        \draw (1.8, -3.4) node[twoportshape, t={\twocm{CH 15}{Repeaters}}, circuitikz/bipoles/twoport/width=1.6, scale=0.5] (rep15) {};
+
+        % Direction switches
+        \draw (4.6, 0.4) node[twoportshape,t=\fourcm{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch0) {};
+        \draw (4.6, -0.4) node[twoportshape,t=\fourcm{Per-channel \phantom{spac} x8 }{Input/Output Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (ioswitch1) {};
+        \begin{scope}[xshift=5cm, yshift=0.65cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4, 0) to[short,-o](0.75, 0);
+            \draw (0.78, 0)-- +(30: 0.46);
+            \draw (1.25, 0)to[short,o-](1.6, 0);
+        \end{scope}
+        \begin{scope}[xshift=5cm, yshift=-0.15cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4, 0) to[short,-o](0.75, 0);
+            \draw (0.78, 0)-- +(30: 0.46);
+            \draw (1.25, 0)to[short,o-](1.6, 0);
+        \end{scope}
+
+        % I2C I/O expanders
+        \draw (4.6, 1.6) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c0) {};
+        \draw (4.6, -1.6) node[twoportshape,t=\fourcm{IO Expander}{for I2C Bus}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (i2c1) {};
+
+        % 2 Aesthetic EEPROMs
+        \draw (4.6, 2.2) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (eeprom0) {};
+        \draw (4.6, -2.2) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=2.7, scale=0.5] (eeprom1) {};
+
+        % EEMs from core device / controllers
+        \draw (7.2, 1.9) node[twoportshape, t={EEM Port 0}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem0) {};
+        \draw (7.2, -1.9) node[twoportshape, t={EEM Port 1}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem1) {};
+
+        % Connect RJ45 to LVDS DIO channels
+        % CH 0
+        \draw [latexslim-] (rep0.west) -- (0.7, 3.4);
+        \draw [-] (0.7, 3.4) -- (0.7, 3.1);
+        \draw [-latexslim] (0.7, 3.1) -- (0.25, 3.1);
+        % CH 1
+        \draw [latexslim-latexslim] (0.25, 2.9) -- (0.9, 2.9);
+        \node [label=center:\tiny{CH 1}] at (1.2, 2.9) {};
+        % CH 2
+        \draw [latexslim-latexslim] (0.25, 2.7) -- (0.9, 2.7);
+        \node [label=center:\tiny{CH 2}] at (1.2, 2.7) {};
+        % CH 3
+        \draw [latexslim-] (rep3.west) -- (0.7, 2.2);
+        \draw [-] (0.7, 2.2) -- (0.7, 2.5);
+        \draw [-latexslim] (0.7, 2.5) -- (0.25, 2.5);
+
+        % CH 4
+        \draw [latexslim-] (rep4.west) -- (0.7, 1.6);
+        \draw [-] (0.7, 1.6) -- (0.7, 1.3);
+        \draw [-latexslim] (0.7, 1.3) -- (0.25, 1.3);
+        % CH 5
+        \draw [latexslim-latexslim] (0.25, 1.1) -- (0.9, 1.1);
+        \node [label=center:\tiny{CH 5}] at (1.2, 1.1) {};
+        % CH 6
+        \draw [latexslim-latexslim] (0.25, 0.9) -- (0.9, 0.9);
+        \node [label=center:\tiny{CH 6}] at (1.2, 0.9) {};
+        % CH 7
+        \draw [latexslim-] (rep7.west) -- (0.7, 0.4);
+        \draw [-] (0.7, 0.4) -- (0.7, 0.7);
+        \draw [-latexslim] (0.7, 0.7) -- (0.25, 0.7);
+
+        % CH 8
+        \draw [latexslim-] (rep8.west) -- (0.7, -0.4);
+        \draw [-] (0.7, -0.4) -- (0.7, -0.7);
+        \draw [-latexslim] (0.7, -0.7) -- (0.25, -0.7);
+        % CH 9
+        \draw [latexslim-latexslim] (0.25, -0.9) -- (0.9, -0.9);
+        \node [label=center:\tiny{CH 9}] at (1.2, -0.9) {};
+        % CH 10
+        \draw [latexslim-latexslim] (0.25, -1.1) -- (0.9, -1.1);
+        \node [label=center:\tiny{CH 10}] at (1.2, -1.1) {};
+        % CH 11
+        \draw [latexslim-] (rep11.west) -- (0.7, -1.6);
+        \draw [-] (0.7, -1.6) -- (0.7, -1.3);
+        \draw [-latexslim] (0.7, -1.3) -- (0.25, -1.3);
+
+        % CH 12
+        \draw [latexslim-] (rep12.west) -- (0.7, -2.2);
+        \draw [-] (0.7, -2.2) -- (0.7, -2.5);
+        \draw [-latexslim] (0.7, -2.5) -- (0.25, -2.5);
+        % CH 13
+        \draw [latexslim-latexslim] (0.25, -2.7) -- (0.9, -2.7);
+        \node [label=center:\tiny{CH 13}] at (1.2, -2.7) {};
+        % CH 14
+        \draw [latexslim-latexslim] (0.25, -2.9) -- (0.9, -2.9);
+        \node [label=center:\tiny{CH 14}] at (1.2, -2.9) {};
+        % CH 15
+        \draw [latexslim-] (rep15.west) -- (0.7, -3.4);
+        \draw [-] (0.7, -3.4) -- (0.7, -3.1);
+        \draw [-latexslim] (0.7, -3.1) -- (0.25, -3.1);
+
+        % Interconnect repeaters controlled by EEM 0
+        \draw [latexslim-] (2.4, 3.5) -- (2.9, 3.5);
+        \draw [latexslim-] (2.4, 2.3) -- (2.9, 2.3);
+        \draw [latexslim-] (2.4, 1.7) -- (2.9, 1.7);
+        \draw [latexslim-] (2.4, 0.5) -- (2.9, 0.5);
+
+        \draw [-] (2.9, 3.5) -- (2.9, 0.5);
+
+        \draw [latexslim-] (2.4, 3.3) -- (3.1, 3.3);
+        \draw [latexslim-] (2.4, 2.1) -- (3.1, 2.1);
+        \draw [latexslim-] (2.4, 1.5) -- (3.1, 1.5);
+        \draw [latexslim-] (2.4, 0.3) -- (3.1, 0.3);
+
+        \draw [-] (3.1, 3.3) -- (3.1, 0.3);
+
+        % Interconnect repeaters controlled by EEM 1
+        \draw [latexslim-] (2.4, -3.5) -- (2.9, -3.5);
+        \draw [latexslim-] (2.4, -2.3) -- (2.9, -2.3);
+        \draw [latexslim-] (2.4, -1.7) -- (2.9, -1.7);
+        \draw [latexslim-] (2.4, -0.5) -- (2.9, -0.5);
+
+        \draw [-] (2.9, -3.5) -- (2.9, -0.5);
+
+        \draw [latexslim-] (2.4, -3.3) -- (3.1, -3.3);
+        \draw [latexslim-] (2.4, -2.1) -- (3.1, -2.1);
+        \draw [latexslim-] (2.4, -1.5) -- (3.1, -1.5);
+        \draw [latexslim-] (2.4, -0.3) -- (3.1, -0.3);
+
+        \draw [-] (3.1, -3.3) -- (3.1, -0.3);
+
+        % Junction between I/O expander and I/O switches
+        \node at (4.6, 1.0)[circle,fill,inner sep=0.7pt]{};
+        \draw [-latexslim] (i2c0.south) -- (4.6, 1.0);
+        \draw [-latexslim] (ioswitch0.north) -- (4.6, 1.0);
+        \draw [-] (4.6, 1.0) -- (3.1, 1.0);
+
+        \node at (4.6, -1.0)[circle,fill,inner sep=0.7pt]{};
+        \draw [-latexslim] (i2c1.north) -- (4.6, -1.0);
+        \draw [-latexslim] (ioswitch1.south) -- (4.6, -1.0);
+        \draw [-] (4.6, -1.0) -- (2.9, -1.0);
+
+        % Connect EEM Ports
+        \draw [-latexslim] (2.9, 2.8) -- (6.85, 2.8);
+        \draw [latexslim-latexslim] (eeprom0.east) -- (6.85, 2.2);
+        \draw [latexslim-latexslim] (i2c0.east) -- (6.85, 1.6);
+
+        \draw [-latexslim] (3.1, -2.8) -- (6.85, -2.8);
+        \draw [latexslim-latexslim] (eeprom1.east) -- (6.85, -2.2);
+        \draw [latexslim-latexslim] (i2c1.east) -- (6.85, -1.6);
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.88}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        % Channel 0 input repeater
+        \draw (3, 3.8) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (rep_in0) {};
+
+        % Extra node to raise the upper boundary of the ch7 dotted area
+        \draw[color=white, text=black] (3, 5.3) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (rep_out0_north) {};
+
+        % Left-extend the dotted area to enclose the intersection between input & output
+        \draw[color=white, text=black] (2.1, 5.2) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (rep_out0_west) {};
+
+        % Right-extend the dotted area to enclose intersection & DIR text
+        \draw[color=white, text=black] (3.8, 5.2) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (rep_out0_east) {};
+
+        % Channel 0 output repeater, defined after previous node to coverup white boundaries
+        \draw (3, 5.0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (rep_out0) {};
+
+        % Channel 0 boundary
+        \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(rep_in0)(rep_out0)(rep_out0_north)(rep_out0_west)(rep_out0_east)] (sig0) {};
+        \node[fill=white, scale=0.7] at (sig0.north) {CH X Repeaters};
+
+        % Channel 0 direction line
+        \draw [latexslim-latexslim] (3, 4.0) -- (3, 4.8);
+        \draw [-] (3, 4.4) -- (4.6, 4.4);
+        \node [label=center:\tiny{CH X}] at (5.0, 4.5) {};
+        \node [label=center:\tiny{Direction}] at (5.0, 4.3) {};
+
+        % Expose & interconnect internal LVDS inputs
+        \node at (3.8, 5.0)[circle,fill,inner sep=0.7pt]{};
+        \draw [latexslim-] (rep_out0.west) -- (3.8, 5.0);
+        \draw [-latexslim] (rep_in0.east) -- (3.8, 3.8) -- (3.8, 5.0);
+        \draw [latexslim-latexslim] (3.8, 5.0) -- (4.6, 5.0);
+        \node [label=center:\tiny{CH X}] at (5.0, 5.1) {};
+        \node [label=center:\tiny{EEM I/O}] at (5.0, 4.9) {};
+
+        % Expose external LVDS I/O
+        \node at (2.1, 4.4)[circle,fill,inner sep=0.7pt]{};
+        \draw [-latexslim] (rep_out0.east) -- (2.1, 5.0) -- (2.1, 4.4);
+        \draw [latexslim-] (rep_in0.west) -- (2.1, 3.8) -- (2.1, 4.4);
+        \draw [latexslim-latexslim] (2.1, 4.4) -- (1.3, 4.4);
+        \node [label=center:\tiny{CH X}] at (0.9, 4.5) {};
+        \node [label=center:\tiny{LVDS I/O}] at (0.9, 4.3) {};
+
+    \end{circuitikz}
+    }
+
+    \caption{Detailed diagram for channel repeaters}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[angle=90, height=1.7in]{photo2245.jpg}
+    \includegraphics[angle=90, height=0.4in]{DIO_RJ45_FP.pdf}
+    \caption{LVDS-TTL card and front panel}
+\end{figure}
+
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{2245 LVDS-TTL}{https://github.com/sinara-hw/DIO_LVDS_RJ45/wiki}
+
+\section{Electrical Specifications}
+
+All specifications are in $-40\degree C \leq T_A \leq 85\degree C$ unless otherwise noted. Information in this section is based on the datasheet of the repeater IC (FIN1101K8X\footnote{\label{repeaters}\url{https://www.onsemi.com/pdf/datasheet/fin1101-d.pdf}}).
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Recommended Input Voltage}
+\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Magnitude of differential input & $|V_{ID}|$ & 0.1 & & 3.3 & V \\
+    \hline
+    Common mode input & $V_{IC}$ & $|V_{ID}|/2$ & & $3.3-|V_{ID}|/2$ & V \\
+    \hline
+    Differential input threshold HIGH & $V_{TH}$ & & & 100 & mV & \\
+    \hline
+    Differential input threshold LOW & $V_{TL}$ & -100 & & & mV & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+All typical values of DC specifications are at $T_A = 25\degree C$.
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{DC Specifications}
+\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Output differential voltage & $V_{OD}$ & 250 & 330 & 450 & mV & \multirow{4}{*}{With 100$\Omega$ load.} \\
+    \cline{0-5}
+    $|V_{OD}|$ change (LOW-to-HIGH) & $\Delta V_{OD}$ & & & 25 & mV & \\
+    \cline{0-5}
+    Offset voltage & $V_{OS}$ & 1.125 & 1.23 & 1.375 & V & \\
+    \cline{0-5}
+    $|V_{OS}|$ change (LOW-to-HIGH) & $\Delta V_{OS}$ & & & 25 & mV & \\
+    \hline
+    Short circuit output current & $I_{OS}$ & & $\pm3.4$ & $\pm6$ & mA & \\
+    \hline
+    Input current & $I_{IN}$ & & & $\pm20$ & \textmu A & Recommended input voltage \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+All typical values of AC specifications are at $T_A = 25\degree C$, $V_{ID} = 300mV$, $V_{IC} = 1.3V$ unless otherwise given.
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{AC Specifications}
+\begin{tabularx}{\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Differential output rise time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & Duty cycle = 50\%.\\
+    (20\% to 80\%) & & & & &    \\
+    \cline{0-5}
+    Differential output fall time & \multirow{2}{*}{0.29} & \multirow{2}{*}{0.40} & \multirow{2}{*}{0.58} & \multirow{2}{*}{ns} & \\
+    (80\% to 20\%) & & & & & \\
+    \cline{0-5}
+    Pulse width distortion & & 0.01 & 0.2 & ns & \\
+    \hline
+    LVDS data jitter, & & \multirow{2}{*}{85} & \multirow{2}{*}{125} & \multirow{2}{*}{ps} & $PRBS=2^{23}-1$\\
+    deterministic & & & & & 800 Mbps\\
+    \hline
+    LVDS clock jitter, & & \multirow{2}{*}{2.1} & \multirow{2}{*}{3.5} & \multirow{2}{*}{ps} & \multirow{2}{*}{400 MHz clock}\\
+    random (RMS) & & & & & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+\section{Configuring IO Direction \& Termination}
+\begin{multicols}{2}
+The IO direction of each channel can be configured by DIP switches, which are found at the top of the card.
+\begin{itemize}
+    \itemsep0em
+    \item IO direction switch closed (\texttt{ON}) \\
+          Fixes the corresponding bank to output. The IO direction cannot be changed by I\textsuperscript{2}C.
+    \item IO direction switch open (OFF) \\
+          The corresponding bank is set to input by default. IO direction \textit{can} be changed by I\textsuperscript{2}C.
+\end{itemize}
+
+\vspace*{\fill}\columnbreak
+\begin{center}
+    \centering
+    \includegraphics[height=1.5in]{lvds_ttl_switches.jpg}
+    \captionof{figure}{Position of switches}
+\end{center}
+\end{multicols}
+
+\newpage
+
+\codesection{2245 LVDS-TTL card}
+
+Timing accuracy in these examples is well under 1 nanosecond thanks to ARTIQ RTIO infrastructure.
+
+\subsection{One pulse per second}
+The channel should be configured as output in both gateware and hardware.
+\inputcolorboxminted{firstline=9,lastline=14}{examples/ttl.py}
+
+\subsection{Morse code}
+This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
+\inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
+
+\newpage
+\subsection{Counting rising edges in a 1ms window}
+The channel should be configured as input in both gateware and hardware.
+\inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
+
+This example code uses the software counter, which has a maximum count rate of approximately 1 million events per second.
+If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
+\inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
+
+\subsection{Responding to an external trigger}
+One channel needs to be configured as input, and the other as output.
+\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
+
+\newcommand{\wrapspacer}[1]% #1 = special text
+{\bgroup
+  \sbox0{\begin{minipage}{\linewidth}\hrule height0pt
+    #1\hrule height0pt
+    \end{minipage}}%
+  \dimen0=\dimexpr \ht0+\dp0\relax
+  \loop\ifdim\dimen0>\baselineskip
+    \strut\vspace{-\baselineskip}\newline
+    \advance\dimen0 by -\baselineskip
+  \repeat
+  \noindent\strut\usebox0\par
+\egroup}
+
+\newpage
+\subsection{SPI Master Device}
+If one of the two card EEM ports is configured as \texttt{dio\char`_spi} instead of \texttt{dio}, its associated TTL channels can be configured as SPI master devices. Invocation of an SPI transfer follows this pattern:
+\begin{enumerate}
+    % The config register can be set using set_config.
+    % However, the only difference between these 2 methods is that set_config accepts an arbitrary
+    % frequency, then translate into the rough frequency divisor for set_config_mu.
+    % It doesn't guarantee such frequency would be set as the SPI frequency
+
+    % In addition, finding clock division is quite easy. set_config_mu seems to be a more
+    % straight-forward & representative of the actual implementation.
+    \item Set the \texttt{config} register (e.g. using \texttt{set\char`_config\char`_mu()}).
+    \item Start the SPI transfer by writing the \texttt{data} register using \texttt{write()}.
+    \item If the data from the SPI slave is to be read (i.e. \texttt{SPI\char`_INPUT} was set in \texttt{config}), invoke \texttt{read()} to read.
+
+\end{enumerate}
+
+The list of configurations supported in the gateware are listed as below:
+
+\begin{table}[h]
+    \centering
+    \begin{tabular}{|c|l|}
+    \hline
+    Flag                                    & Description                                                             \\ \hline
+    \texttt{SPI\char`_OFFLINE}              & Switch all pins to high impedance mode.                                 \\ \hline
+    \texttt{SPI\char`_END}                  & Next SPI transfer is the last of the transcation.                       \\ \hline
+    \texttt{SPI\char`_INPUT}                & Submit SPI read data as RTIO input event when the transfer is complete. \\ \hline
+    \texttt{SPI\char`_CS\char`_POLARITY}    & Active level of chip select (CS)                                        \\ \hline
+    \texttt{SPI\char`_CLK\char`_POLARITY}   & Idle level of serial clock (SCK)                                        \\ \hline
+    \texttt{SPI\char`_CLK\char`_PHASE}      & Data is sampled on falling edge \& shifted out on rising edge.          \\ \hline
+    \texttt{SPI\char`_LSB\char`_FIRST}      & LSB is the first on bit on the wire.                                    \\ \hline
+    \texttt{SPI\char`_HALF\char`_DUPLEX}    & Use 3-wire SPI, where MOSI is both input \& output capable.             \\ \hline
+    \end{tabular}
+\end{table}
+
+The following ARTIQ example demonstrates the flow of an SPI transaction on a typical SPI setup with 3 homogeneous slaves.
+The direction switches on the LVDS-TTL card should be set to the correct IO direction for all relevant channels before powering on.
+\begin{center}
+    \begin{circuitikz}[european, scale=1, every label/.append style={align=center}]
+        % SPI master
+        \draw (0, 1.8) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=2, scale=1] (master) {};
+        \node [label={center:\large{SPI Master}}] at (-0.6, 2.05) {};
+        \node [label={center:\large{(LVDS-TTL)}}] at (-0.6, 1.55) {};
+        \node [label=left:{SCK}] at (2, 2.8) {};
+        \node [label=left:{MOSI}] at (2, 2.4) {};
+        \node [label=left:{MISO}] at (2, 2.0) {};
+        \node [label=left:{CS0}] at (2, 1.6) {};
+        \node [label=left:{CS1}] at (2, 1.2) {};
+        \node [label=left:{CS2}] at (2, 0.8) {};
+
+        % SPI slaves
+        % The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
+        \draw (7, 2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave0) {};
+        \node [label={center:\large{SPI Slave 0}}] at (7.6, 2.2) {};
+        \node [label=right:{SCK}] at (5, 2.8) {};
+        \node [label=right:{MOSI}] at (5, 2.4) {};
+        \node [label=right:{MISO}] at (5, 2.0) {};
+        \node [label=right:{$\mathrm{\overline{CS}}$}] at (5, 1.6) {};
+
+        % The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
+        \draw (7, 0) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave1) {};
+        \node [label={center:\large{SPI Slave 1}}] at (7.6, 0) {};
+        \node [label=right:{SCK}] at (5, 0.6) {};
+        \node [label=right:{MOSI}] at (5, 0.2) {};
+        \node [label=right:{MISO}] at (5, -0.2) {};
+        \node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -0.6) {};
+
+        % The top one will have its SCK, MOSI, MISO aligned with the master, for wiring simplicity
+        \draw (7, -2.2) node[twoportshape, t={}, circuitikz/bipoles/twoport/width=2.8, circuitikz/bipoles/twoport/height=1.4, scale=1] (slave2) {};
+        \node [label={center:\large{SPI Slave 2}}] at (7.6, -2.2) {};
+        \node [label=right:{SCK}] at (5, -1.6) {};
+        \node [label=right:{MOSI}] at (5, -2.0) {};
+        \node [label=right:{MISO}] at (5, -2.4) {};
+        \node [label=right:{$\mathrm{\overline{CS}}$}] at (5, -2.8) {};
+
+        % Connect the master to slave 0
+        \draw [-latexslim] (1.95, 2.8) -- (5.05, 2.8);
+        \draw [-latexslim] (1.95, 2.4) -- (5.05, 2.4);
+        \draw [latexslim-] (1.95, 2.0) -- (5.05, 2.0);
+        \draw [-latexslim] (1.95, 1.6) -- (5.05, 1.6);
+
+        % Connect slave 1
+        \draw [-latexslim] (4.2, 2.8) -- (4.2, 0.6) -- (5.05, 0.6);
+        \draw [-latexslim] (3.8, 2.4) -- (3.8, 0.2) -- (5.05, 0.2);
+        \draw [-] (3.4, 2.0) -- (3.4, -0.2) -- (5.05, -0.2);
+        \draw [-latexslim] (1.95, 1.2) -- (3.0, 1.2) -- (3.0, -0.6) -- (5.05, -0.6);
+
+        % Connect slave 2
+        \draw [-latexslim] (4.2, 0.6) -- (4.2, -1.6) -- (5.05, -1.6);
+        \draw [-latexslim] (3.8, 0.2) -- (3.8, -2.0) -- (5.05, -2.0);
+        \draw [-] (3.4, -0.2) -- (3.4, -2.4) -- (5.05, -2.4);
+        \draw [-latexslim] (1.95, 0.8) -- (2.6, 0.8) -- (2.6, -2.8) -- (5.05, -2.8);
+
+        % Add dot to intersection to distinguish from overlaps
+        \node at (4.2, 2.8)[circle,fill,inner sep=0.7pt]{};
+        \node at (3.8, 2.4)[circle,fill,inner sep=0.7pt]{};
+        \node at (3.4, 2.0)[circle,fill,inner sep=0.7pt]{};
+        \node at (4.2, 0.6)[circle,fill,inner sep=0.7pt]{};
+        \node at (3.8, 0.2)[circle,fill,inner sep=0.7pt]{};
+        \node at (3.4, -0.2)[circle,fill,inner sep=0.7pt]{};
+
+    \end{circuitikz}
+\end{center}
+
+\newpage
+\subsubsection{SPI Configuration}
+The following examples will assume the SPI communication has the following properties:
+\begin{itemize}
+    \item Chip select (CS) is active low
+    \item Serial clock (SCK) idle level is low
+    \item Data is sampled on rising edge of SCK \& shifted out on falling edge of SCK
+    \item Most significant bit (MSB) first
+    \item Full duplex
+\end{itemize}
+The baseline configuration for an \texttt{SPIMaster} instance can be defined as such:
+\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
+The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
+
+\subsubsection{SPI frequency}
+Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor in [2, 257]. In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
+\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
+
+\subsubsection{SPI write}
+Typically, an SPI write operation involves sending an instruction and data to the SPI slaves. Suppose the instruction and data are 8 bits and 32 bits respectively. The timing diagram of such a write operation is shown in the following:
+
+\begin{center}
+\begin{tikztimingtable}
+    [
+        timing/d/background/.style={fill=white},
+        timing/lslope=0.2
+    ]
+        $\mathrm{\overline{CS}}$ & H51{L}H \\
+        SCK     & LL31{T}; 2{[dotted] T}; 17{T} L \\
+        % The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
+        % then print the label from macro. But it turns out tikz-timing will print
+        % the counter value separately, even with an additional macro.
+        % Therefore, it does not work properly.
+        MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}, timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
+        UJ{7}8{2I}R{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
+        MOSI & 53U \\
+\end{tikztimingtable}%
+\end{center}
+
+\newpage
+Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transaction can be performed with the following code:
+\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
+
+\subsubsection{SPI read}
+A 32-bit read is represented by the following timing diagram:
+
+\begin{center}
+\begin{tikztimingtable}
+    [
+        timing/d/background/.style={fill=white},
+        timing/lslope=0.2
+    ]
+        $\mathrm{\overline{CS}}$ & H51{L}H \\
+        SCK     & LL31{T}; 2{[dotted] T}; 17{T} L \\
+        % The better approach is to use pass the counter (\tikztimingcounter{Q}) to a macro,
+        % then print the label from macro. But it turns out tikz-timing will print
+        % the counter value separately, even with an additional macro.
+        % Therefore, it does not work properly.
+        MOSI & [timing/counter/new={char=I, reset char=J, reset type=arg, increment=-1, text format=I}]
+        UJ{7}8{2I}36U \\
+        MOSI & [timing/counter/new={char=A, reset char=R, reset type=arg, increment=-1, text format=D}]
+        17UR{31}8{2A}; [dotted] D [dotted] D{}; R{7}8{2A}2U \\
+\end{tikztimingtable}%
+\end{center}
+
+Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
+\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
+
+\newpage
+\ordersection{2245 LVDS-TTL}
+
+\finalfootnote
+
+\end{document}

4456.tex

@@ -0,0 +1,433 @@
+\input{preamble.tex}
+\graphicspath{{images/4456}{images}}
+
+\title{4456 Synthesizer Mirny}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{4-channel VCO/PLL}
+\item{Output frequency ranges from 53 MHz to \textgreater 4 GHz}
+\item{Up to 13.6 GHz with Almazny mezzanine}
+\item{Higher frequency resolution than Urukul}
+\item{Lower jitter and phase noise}
+\item{Large frequency changes take several milliseconds}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Low-noise microwave source}
+\item{Quantum state control}
+\item{Driving acousto/electro-optic modulators}
+\end{itemize}
+
+\section{General Description}
+The 4456 Synthesizer Mirny card is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds microwave generation capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+It provides 4 channels of PLL frequency synthesis. Output frequencies from 53 MHz to \textgreater 4 GHz are supported.The range can be expanded up to 13.6 GHz with the Almazny mezzanine (4467 HF Synthesizer).
+
+Each channel can be attenuated from 0 to -31.5 dB by a digital attenuator. RF switches on each channel provides at least 50 dB isolation.
+
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.95}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        \begin{scope}[]
+
+            % Node to pin-point the locations of SMA symbols
+            \draw[color=white, text=black] (-0.1, 0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (ext_clk) {};
+            \draw[color=white, text=black] (-0.1, 0) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx) {};
+            \draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf0) {};
+            \draw[color=white, text=black] (-0.1, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf1) {};
+            \draw[color=white, text=black] (-0.1, -3.15) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf2) {};
+            \draw[color=white, text=black] (-0.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (rf3) {};
+
+            % Node to pin-point the locations of SMP symbols
+            \draw[color=white, text=black] (2.65, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp0) {};
+            \draw[color=white, text=black] (2.65, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp1) {};
+            \draw[color=white, text=black] (2.65, -3.15) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp2) {};
+            \draw[color=white, text=black] (2.65, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (smp3) {};
+
+            % Extra node to expand the future channel dotted area eastward
+            \draw[color=white, text=black] (2.1, -3.85) node[twoportshape, circuitikz/bipoles/twoport/width=0.4, scale=0.4 ] (sig3_east) {};
+
+            % Labels for female EXT_CLK, MMCX, RF {0, 1, 2, 3}
+            \node [label=left:\tiny{EXT CLK}] at (0.35, 0.35) {};
+            \node [label=left:\tiny{MMCX}] at (0.35, 0) {};
+            \node [label=left:\tiny{RF 0}] at (0.35, -1.75) {};
+            \node [label=left:\tiny{RF 1}] at (0.35, -2.45) {};
+            \node [label=left:\tiny{RF 2}] at (0.35, -3.15) {};
+            \node [label=left:\tiny{RF 3}] at (0.35, -3.85) {};
+
+            % draw female EXT_CLK, MMCX, RF {0, 1, 2, 3}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-5cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=0cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=35cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=45cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=55cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+
+            % draw female SMP connectors
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-25cm, yshift=-45cm]
+                \draw (0,0) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-35cm, yshift=-45cm]
+                \draw (0,0) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-45cm, yshift=-45cm]
+                \draw (0,0) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-55cm, yshift=-45cm]
+                \draw (0,0) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+            \end{scope}
+
+            % Labels for female SMP {0, 1, 2, 3}
+            \node [label=right:\tiny{SMP 0}] at (3, -1.75) {};
+            \node [label=right:\tiny{SMP 1}] at (3, -2.45) {};
+            \node [label=right:\tiny{SMP 2}] at (3, -3.15) {};
+            \node [label=right:\tiny{SMP 3}] at (3, -3.85) {};
+
+            % Draw the internal oscillator
+            \draw (0.02, -0.45) node[twoportshape, t={OSC}, circuitikz/bipoles/twoport/width=0.8, scale=0.4] (xo) {};
+
+            % Draw the clock buffers
+            \draw (1.6, 0) node[twoportshape, t={CLK Buffers}, circuitikz/bipoles/twoport/width=2.2, scale=0.5, rotate=-90] (clk_buf) {};
+
+            % Connect CLK_IN to PLL clock buffers
+            \draw [-latexslim] (ext_clk.east) -- (1.35, 0.35);
+            \draw [-latexslim] (mmcx.east) -- (1.35, 0);
+            \draw [-latexslim] (xo.east) -- (1.35, -0.45);
+
+            % Connect CPLD clk_sel to PLL clock buffers
+            \draw [-latexslim] (clk_buf.east) -- (1.6, -1.35);
+
+            % Signal path: From control signals / clock of PLL to output of the RF switches
+            \draw (1.6, -1.75) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig0) {};
+            \draw (1.6, -2.45) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig1) {};
+            \draw (1.6, -3.15) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig2) {};
+            \draw (1.6, -3.85) node[twoportshape, t={PLL Signal Path}, circuitikz/bipoles/twoport/width=2, scale=0.5] (sig3) {};
+
+            % Connect RF to PLL block
+            \draw [latexslim-] (rf0.east) -- (sig0.west);
+            \draw [latexslim-] (rf1.east) -- (sig1.west);
+            \draw [latexslim-] (rf2.east) -- (sig2.west);
+            \draw [latexslim-] (rf3.east) -- (sig3.west);
+
+            % PLL signal path dotted area
+            \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(rf3)(sig0)(sig3_east.east)] (abs_dds) {};
+            \node[fill=white, rotate=-90, scale=0.7] at (abs_dds.west) {PLL Channels};
+
+            % CPLD after signal path 0
+            \draw (4.6, -0.2) node[twoportshape, t={CPLD}, circuitikz/bipoles/twoport/width=1.1, scale=0.8, rotate=-90] (cpld) {};
+
+            % Connect CPLD to:
+            %   PLL clock buffer
+            \draw [latexslim-] (clk_buf.north) -- (4.2, 0);
+            %   PLL signal path
+            \draw [latexslim-latexslim] (4.2, -0.4) -- (2.2, -0.4) -- (2.2, -1.35);
+
+            % Connect each PLL channel to its cooresponding SMP connector
+            \draw [-latexslim] (sig0.east) -- (smp0.east);
+            \draw [-latexslim] (sig1.east) -- (smp1.east);
+            \draw [-latexslim] (sig2.east) -- (smp2.east);
+            \draw [-latexslim] (sig3.east) -- (smp3.east);
+
+            % Draw AFE header
+            \draw (4.6, -2.8) node[twoportshape, t={AFE Header}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (afe) {};
+
+            % Connect AFE header to CPLD
+            \draw [latexslim-latexslim] (cpld.east) -- (afe.west);
+
+            % Draw LVDS transceivers, EEM
+            \draw (6.2, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
+            \draw (6.2, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
+            \draw (7.8, -1.5) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.8, scale=0.7, rotate=-90] (eem) {};
+
+            % Connect LVDS transceiver to CPLD
+            \draw [latexslim-latexslim] (lvds0.south) -- (5, 0);
+            \draw [latexslim-latexslim] (lvds1.south) -- (5.5, -1.6) -- (5.5, -0.4) -- (5, -0.4);
+
+            % Connect EEM to LVDS transceiver
+            \draw [latexslim-latexslim] (lvds0.north) -- (7.45, 0);
+            \draw [latexslim-latexslim] (lvds1.north) -- (7.45, -1.6);
+
+            % Draw EEPROM
+            \draw (6.2, -3.85) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (eeprom) {};
+
+            % Interconnect I2C between EEPROM, AFE header & EEM
+            \draw [latexslim-latexslim] (afe.north) -- (7.45, -2.8);
+            \draw [-latexslim] (6.2, -2.8) -- (eeprom.north);
+
+        \end{scope}
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.88}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        \begin{scope}[]
+            % RF switches {0, 1, 2, 3} for SMA {0, 1, 2, 3}
+            \draw (1.4, 0) node[twoportshape, t={RF Switch}, circuitikz/bipoles/twoport/width=1.5, scale=0.6] (sw) {};
+
+            % Amplifiers {0, 1, 2, 3} for RF switches {0, 1, 2, 3}
+            \draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
+
+            % Attenuators {0, 1, 2, 3} for amplifiers {0, 1, 2, 3}
+            \draw (4.6, 0) node[twoportshape, t=\fourcm{Digital}{Attenuator}, circuitikz/bipoles/twoport/width=2, scale=0.6, rotate=-90] (att) {};
+
+            % PLL {0, 1, 2, 3} for attenuators {0, 1, 2, 3}
+            \draw (6.6, 0) node[twoportshape, t={PLL}, circuitikz/bipoles/twoport/width=1.2, scale=0.7] (pll) {};
+
+            % Connect main signal path
+            \draw [-latexslim] (pll.west) -- (att.north);
+            \draw [-latexslim] (att.south) -- (amp.west);
+            \draw [-latexslim] (amp.east) -- (sw.east);
+
+            % Connect abstract PLL clock input
+            \node [label=above:\tiny{CLK Buffers}] at (8, -0.2) {};
+            \draw [latexslim-] (pll.east) -- (8, 0);
+
+            % Insert CPLD signal to relevant components
+            \node [label=above:\tiny{CPLD}] at (8, 1.1) {};
+            \draw [-] (1.4, 1.3) -- (8, 1.3);
+            \draw [-latexslim] (1.4, 1.3) -- (sw.north);
+            \draw [-latexslim] (4.6, 1.3) -- (att.west);
+            \draw [-latexslim] (6.6, 1.3) -- (pll.north);
+
+            % Connect PLL to SMP connectors
+            \draw [-latexslim] (pll.south) -- (6.6, -1.35);
+            \node [label=below:\tiny{SMP}] at (6.6, -1.15) {};
+
+            % Direct the RF switch output to RF output
+            \draw [-latexslim] (sw.west) -- (0, 0);
+            \node [label=left:\tiny{RF}] at (0.2, 0) {};
+
+        \end{scope}
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified PLL Signal Path}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2in]{photo4456.jpg}
+    \includegraphics[height=3in, angle=90]{Mirny_FP.pdf}
+    \caption{Mirny card and front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{4456 Synthesizer Mirny}{https://github.com/sinara-hw/mirny}
+
+\section{Electrical Specifications}
+
+Specifications of parameters are based on the datasheets of the PLL IC
+(ADF5356\footnote{\label{adf5356}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5356.pdf}}),
+clock buffer IC (Si53340-B-GM\footnote{\label{clock_buffer}\url{https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si5334x-datasheet.pdf}}),
+and digital attenuator IC (HMC542BLP4E\footnote{\label{attenuator}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/hmc542b.pdf}}).
+Test results are from Krzysztof Belewicz's thesis. "Microwave synthesizer for driving ion traps in quantum computing"\footnote{\label{mirny_thesis}\url{https://m-labs.hk/Krzysztof\_Belewicz\_V1.1.pdf}}.
+
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Recommended Operating Conditions}
+\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    % Note to future editors, the clk_div signal in gateware is not used.
+    % Input divider was removed (mirny#8)
+    Clock input & & & & & \\
+        \hspace{3mm}Frequency\repeatfootnote{adf5356}
+            & 10 & & 250 & MHz & Single-ended clock input (PLL config.) \\
+            & 10 & & 600 & MHz & Differential clock input (PLL config.) \\
+        \cline{2-6}
+        \hspace{3mm}Differential input swing\repeatfootnote{clock_buffer}
+            & 0.11 & & 1.55 & V\textsubscript{p-p} & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Output Specifications}
+\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Frequency & 53.125 &  & 4000 & MHz & \\
+    \hline
+    Digital attenuation\repeatfootnote{attenuator} & -31.5 & & 0 & dB & \\
+    \hline
+    Resolution & \multicolumn{4}{c|}{} & \\
+    \hspace{3mm} Frequency\repeatfootnote{adf5356} & \multicolumn{4}{c|}{52 bits} & \\
+    \hspace{3mm} Phase offset\repeatfootnote{adf5356} & \multicolumn{4}{c|}{24 bits} & \\
+    \hspace{3mm} Digital attenuation\repeatfootnote{attenuator} & \multicolumn{4}{c|}{0.5 dB} & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+Phase noise performance of Mirny was tested using the ADF4351 evaluation kit\repeatfootnote{mirny_thesis}. The SPI signal was driven by the evaluation kit, converted into LVDS signal by propagating through the DIO-tester card, finally arriving at the Mirny card. Mirny was then connected to the RSA5100A spectrum analyzer for measurement.
+
+Noise response spike can be improved by inserting an additional common-mode choke between the power supply and Mirny; note that this common-mode choke is not present on the card itself. The following is a comparison between the two setups at 1 GHz output:
+\begin{itemize}
+    \item Red: Before any modifications
+    \item Blue: CM choke added with an 100 \textmu F capacitor after the CM choke
+\end{itemize}
+
+\begin{figure}[H]
+    \centering
+    \includegraphics[height=3in]{mirny_phase_noise_cm_choke.png}
+    \caption{Phase noise measurement at 1 GHz}
+\end{figure}
+
+Phase noise at different output frequencies is then measured:
+
+\newcolumntype{Y}{>{\centering\arraybackslash}X}
+
+\begin{table}[hbt!]
+\centering
+\begin{threeparttable}
+\caption{Phase noise performance}
+\begin{tabularx}{0.8\textwidth}{| c | Y | Y | Y | Y | Y |}
+    \thickhline
+    \multirow{2}{*}{\textbf{Output frequency}} &
+    \multicolumn{5}{c|}{\textbf{Phase noise (dBc/Hz) at carrier offset}}\\
+    \cline{2-6} & 1 kHz & 10 kHz & 100 kHz & 1 MHz & 10 MHz \\
+    \hline
+    125 MHz & -114 & -116 & -115 & -132 & -133 \\
+    \hline
+    500 MHz & -107 & -129 & -111 & -130 & -132 \\
+    \hline
+    1 GHz & -102 & -106 & -107 & -125 & -133 \\
+    \hline
+    2 GHz & -102 & -98 & -104 & -123 & -124 \\
+    \hline
+    3.5 GHz & -96 & -101 & -103 & -127 & -128 \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+\begin{figure}[H]
+    \centering
+    \includegraphics[height=3in]{mirny_phase_noise_frequency.png}
+    \caption{Phase noise measurement}
+\end{figure}
+
+\codesection{4456 Synthesizer Mirny}
+
+\subsection{1 GHz sinusoidal wave}
+Generates a 1 GHz sinusoid from RF0 with full scale amplitude, attenuated by 12 dB. Both the CPLD and the PLL channels should be initialized.
+
+\inputcolorboxminted{firstline=10,lastline=17}{examples/pll.py}
+
+\subsection{ADF5356 power control}
+Output power can be controlled be configuring the PLL channels individually in addition to the digital attenuators. After initialization of the PLL channel (ADF5356), the following line of code can change the output power level:
+
+\inputcolorboxminted{firstline=28,lastline=28}{examples/pll.py}
+
+The parameter corresponds to a specific change of output power according to the following table\repeatfootnote{adf5356}.
+
+\begin{center}
+    \captionof{table}{Power changes from ADF5356}
+    \begin{tabular}{|c|c|}
+    \hline
+    Parameter & Power \\ \hline
+    0 & -4 dBm \\ \hline
+    1 & -1 dBm \\ \hline
+    2 & +2 dBm \\ \hline
+    3 & +5 dBm \\ \hline
+    \end{tabular}
+\end{center}
+
+ADF5356 gives +5 dBm by default. The stored parameter in ADF5356 can be read using the following line"
+
+\inputcolorboxminted{firstline=29,lastline=29}{examples/pll.py}
+
+\subsection{Periodic 100\textmu s pulses}
+The output can be toggled on and off periodically using the RF switches. The following code emits a 100\textmu s pulse in every millisecond. A microwave signal should be programmed in prior (such as the 1 GHz wave example).
+
+\inputcolorboxminted{firstline=42,lastline=44}{examples/pll.py}
+
+\ordersection{4456 Synthesizer Mirny}
+
+\finalfootnote
+
+\end{document}

5108.tex

@@ -0,0 +1,681 @@
+\include{preamble.tex}
+\graphicspath{{images/5108}{images}}
+
+\title{5108 ADC Sampler}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{8-channel ADC.}
+\item{16-bits resolution.}
+\item{1.5 MSPS simultaneously on all channels.}
+\item{Full scale input voltage $\pm$10mV to $\pm$10V.}
+\item{BNC connector.}
+\item{SMA breakout with 5528 SMA-IDC adapter.}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Sample intermediate-frequency (IF) waveform.}
+\item{Monitor laser power with a photodiode.}
+\item{Synchronize laser frequencies with a phase frequency detector.}
+\item{Form a laser intensity servo with 4410 Urukul.}
+\end{itemize}
+
+\section{General Description}
+The 5108 ADC Sampler is a 8hp EEM module part of the ARTIQ Sinara family.
+It adds analog-digital converting capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+It provides 8 analog-to-digital channels, each exposed by a BNC connector.
+Each channel supports input voltage ranges from \textpm 10mV to \textpm 10V.
+All channels can be sampled simultaneously.
+Channels can broken out to SMA by adding a 5528 SMA-IDC card.
+
+5108 ADC Sampler provides a sample rate of 1.5 MSPS.
+However, the sample rate in practice is typically limited by the use of ARTIQ-Python kernel code.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{1}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        % Node to pin-point the locations of BNC symbols
+        \draw[color=white, text=black] (-0.1, 1.225) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc0) {};
+        \draw[color=white, text=black] (-0.1, 0.875) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc1) {};
+        \draw[color=white, text=black] (-0.1, 0.525) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc2) {};
+        \draw[color=white, text=black] (-0.1, 0.175) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc3) {};
+
+        \draw[color=white, text=black] (-0.1, -0.175) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc4) {};
+        \draw[color=white, text=black] (-0.1, -0.525) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc5) {};
+        \draw[color=white, text=black] (-0.1, -0.875) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc6) {};
+        \draw[color=white, text=black] (-0.1, -1.225) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (bnc7) {};
+
+        % Labels for BNC 0-7
+        \node [label=left:\tiny{IN 0}] at (0.35, 1.225) {};
+        \node [label=left:\tiny{IN 1}] at (0.35, 0.875) {};
+        \node [label=left:\tiny{IN 2}] at (0.35, 0.525) {};
+        \node [label=left:\tiny{IN 3}] at (0.35, 0.175) {};
+        \node [label=left:\tiny{IN 4}] at (0.35, -0.175) {};
+        \node [label=left:\tiny{IN 5}] at (0.35, -0.525) {};
+        \node [label=left:\tiny{IN 6}] at (0.35, -0.875) {};
+        \node [label=left:\tiny{IN 7}] at (0.35, -1.225) {};
+
+        % draw BNC 0-7
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=2.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=7.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=12.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=17.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=-2.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=-7.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=-12.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+        \begin{scope}[scale=0.07 , rotate=-90, xshift=-17.5cm, yshift=2cm]
+            \draw (0,0.65) -- (0,3);
+            \clip (-1.5,0) rectangle (1.5,1.5);
+            \draw (0,0) circle(1.5);
+            \clip (-0.8,0) rectangle (0.8,0.8);
+            \draw (0,0) circle(0.8);
+        \end{scope}
+
+        % Draw termination switches
+        \draw (1.0, 1.925) node[twoportshape,t=\fourcm{100k/50\textOmega}{Switch \phantom{s} x8}, circuitikz/bipoles/twoport/width=1.5, scale=0.5] (termswitch) {};
+        \begin{scope}[xshift=1.2cm, yshift=1.925cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+            \draw (0.4,0) to[short,-o](0.75,0);
+            \draw (0.78,0)-- +(30:0.46);
+            \draw (1.25,0)to[short,o-](1.6,0)   ;   
+        \end{scope}
+
+        % Dwar IDC Port (ADC IN)
+        \draw (0.8, -1.925) node[twoportshape,t={IDC Port}, circuitikz/bipoles/twoport/width=1.5, scale=0.5] (idc) {};
+
+        % Draw PGIAs
+        % The connections are too complicated for the usual buffer/op-amp symbol
+        \draw (3, 2.45) node[twoportshape,t=\fourcm{CH 0}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia0) {};
+        \draw (3, 1.75) node[twoportshape,t=\fourcm{CH 1}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia1) {};
+        \draw (3, 1.05) node[twoportshape,t=\fourcm{CH 2}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia2) {};
+        \draw (3, 0.35) node[twoportshape,t=\fourcm{CH 3}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia3) {};
+        \draw (3, -0.35) node[twoportshape,t=\fourcm{CH 4}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia4) {};
+        \draw (3, -1.05) node[twoportshape,t=\fourcm{CH 5}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia5) {};
+        \draw (3, -1.75) node[twoportshape,t=\fourcm{CH 6}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia6) {};
+        \draw (3, -2.45) node[twoportshape,t=\fourcm{CH 7}{PGIA}, circuitikz/bipoles/twoport/width=1.2, scale=0.5] (pgia7) {};
+
+        % Draw termination connection to input lines
+        \draw [-] (0.65, 1.675) -- (0.65, 1.225);
+        \draw [-] (0.75, 1.675) -- (0.75, 0.875);
+        \draw [-] (0.85, 1.675) -- (0.85, 0.525);
+        \draw [-] (0.95, 1.675) -- (0.95, 0.175);
+        \draw [-] (1.05, 1.675) -- (1.05, -0.175);
+        \draw [-] (1.15, 1.675) -- (1.15, -0.525);
+        \draw [-] (1.25, 1.675) -- (1.25, -0.875);
+        \draw [-] (1.35, 1.675) -- (1.35, -1.225);
+
+        % Draw IDC port (ADC IN) connection to input lines
+        \draw [-] (0.45, -1.675) -- (0.45, 1.225);
+        \draw [-] (0.55, -1.675) -- (0.55, 0.875);
+        \draw [-] (0.65, -1.675) -- (0.65, 0.525);
+        \draw [-] (0.75, -1.675) -- (0.75, 0.175);
+        \draw [-] (0.85, -1.675) -- (0.85, -0.175);
+        \draw [-] (0.95, -1.675) -- (0.95, -0.525);
+        \draw [-] (1.05, -1.675) -- (1.05, -0.875);
+        \draw [-] (1.15, -1.675) -- (1.15, -1.225);
+
+        % Connect BNC to PGIA, with termination line
+        \draw [-latexslim] (bnc0.east) -- (1.9, 1.225) -- (1.9, 2.45) -- (pgia0.west);
+        \draw [-latexslim] (bnc1.east) -- (2, 0.875) -- (2, 1.75) -- (pgia1.west);
+        \draw [-latexslim] (bnc2.east) -- (2.1, 0.525) -- (2.1, 1.05) -- (pgia2.west);
+        \draw [-latexslim] (bnc3.east) -- (2.2, 0.175) -- (2.2, 0.35) -- (pgia3.west);
+        \draw [-latexslim] (bnc4.east) -- (2.2, -0.175) -- (2.2, -0.35) -- (pgia4.west);
+        \draw [-latexslim] (bnc5.east) -- (2.1, -0.525) -- (2.1, -1.05) -- (pgia5.west);
+        \draw [-latexslim] (bnc6.east) -- (2, -0.875) -- (2, -1.75) -- (pgia6.west);
+        \draw [-latexslim] (bnc7.east) -- (1.9, -1.225) -- (1.9, -2.45) -- (pgia7.west);
+
+        % Draw shift register & ADC
+        \draw (4.7, 1) node[twoportshape,t=\fourcm{Shift}{Registers}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (sr) {};
+        \draw (4.7, -1) node[twoportshape,t={ADC}, circuitikz/bipoles/twoport/width=1.6, scale=0.6, rotate=-90] (adc) {};
+
+        % Connect PGIA -> ADC paths
+        \draw [-] (3.45, 2.55) -- (4, 2.55) -- (4, -1);
+        \draw [-] (3.45, -2.35) -- (4, -2.35) -- (4, -1);
+        \draw [-] (3.45, 1.85) -- ++ (0.55, 0);
+        \draw [-] (3.45, 1.15) -- ++ (0.55, 0);
+        \draw [-] (3.45, 0.45) -- ++ (0.55, 0);
+        \draw [-] (3.45, -0.25) -- ++ (0.55, 0);
+        \draw [-latexslim] (3.45, -0.95) -- ++ (0.95, 0);
+        \draw [-] (3.45, -1.65) -- ++ (0.55, 0);
+
+        % Connect SR -> PGIA paths
+        \draw [latexslim-] (3.45, 2.35) -- (3.8, 2.35) -- (3.8, 1);
+        \draw [latexslim-] (3.45, -2.55) -- (3.8, -2.55) -- (3.8, 1);
+        \draw [latexslim-] (3.45, 1.65) -- ++ (0.35, 0);
+        \draw [latexslim-] (3.45, 0.95) -- ++ (0.95, 0);
+        \draw [latexslim-] (3.45, 0.25) -- ++ (0.35, 0);
+        \draw [latexslim-] (3.45, -0.45) -- ++ (0.35, 0);
+        \draw [latexslim-] (3.45, -1.15) -- ++ (0.35, 0);
+        \draw [latexslim-] (3.45, -1.85) -- ++ (0.35, 0);
+
+        % Draw LVDS transceivers & repeaters
+        \draw (6.3, 1) node[twoportshape,t=\fourcm{LVDS}{Transceivers}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (lvds) {};
+        \draw (6.3, -1) node[twoportshape,t={Repeaters}, circuitikz/bipoles/twoport/width=1.8, scale=0.6, rotate=-90] (rep) {};
+
+        % ADC & SR connection lines
+        % Note: MISO line from shift register ignored, the repeater is omiited in some versions
+        % Also, that MISO line does not do anything useful. The ARTIQ driver implementation is just a huge data integrity check.
+        \draw [-latexslim] (6, 1.2) -- (5, 1.2);
+        \draw [-latexslim] (6, 0.8) -- (5.5, 0.8) -- (5.5, -0.8) -- (5, -0.8);
+        % Data comes out of the ADC, the only signal that goes in is the clock
+        \draw [-latexslim] (5, -1.2) -- (6, -1.2);
+
+        % Draw EEPROMs
+        \draw (6, 2.35) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.4, scale=0.6] (eeprom0) {};
+        \draw (6.3, -2.6) node[twoportshape,t={EEPROM}, circuitikz/bipoles/twoport/width=1.4, scale=0.6, rotate=-90] (eeprom1) {};
+
+        % Draw EEM 0 & 1
+        \draw (7.9, 1.9) node[twoportshape,t={EEM Port 0}, circuitikz/bipoles/twoport/width=3.4, scale=0.6, rotate=-90] (eem0) {};
+        \draw (7.9, -1.9) node[twoportshape,t={EEM Port 1}, circuitikz/bipoles/twoport/width=2.6, scale=0.6, rotate=-90] (eem1) {};
+
+        % Connect EEM Port 1
+        \draw [-latexslim] (6.6, -1.2) -- (7.6, -1.2);
+        \draw [latexslim-latexslim] (eeprom1.north) -- (7.6, -2.6);
+
+        % Connect EEM Port 0
+        \draw [-latexslim] (6.6, -0.8) -- (7.1, -0.8) -- (7.1, 0.8) -- (7.6, 0.8);
+        \draw [latexslim-] (6.6, 1.2) -- (7.6, 1.2);
+        \draw [latexslim-latexslim] (eeprom0.east) -- (7.6, 2.35);
+
+        % Draw IO Expander
+        \draw (3, 3.15) node[twoportshape,t={IO Expander}, circuitikz/bipoles/twoport/width=1.8, scale=0.5] (i2c) {};
+
+        % Connect IO Expander
+        \draw [-latexslim] (termswitch.north) -- (1, 3.15) -- (i2c.west);
+        \draw [-latexslim] (i2c.east) -- (7.6, 3.15);
+
+        % Stress that the termination status I2C interface is read-only
+        \node [label=center:\tiny{Read Only}] at (1.6, 3.25) {};
+
+        % State that PGIA stands for "Programmable Gain Instrumentation Amplifier"
+        % The name is too long, and there isn't any good places to mention this
+        \node [label=center:\tiny{Note: PGIA = Programmable Gain Instrumentation Amplifier}] at (3, -3) {};
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[h]
+    \centering
+    \includegraphics[height=1.9in]{Sampler_FP.jpg}
+    \includegraphics[height=1.9in]{photo5108.jpg}
+    \caption{Sampler Card photo}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\section{Electrical Specifications}
+
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Input Specifications}
+\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Input voltage & -10 & & 10 & V & 1x gain, termination off* \\
+     & -1 & & 1 & V & 10x gain\\
+     & -100 & & 100 & mV & 100x gain\\
+     & -10 & & 10 & mV & 1000x gain\\
+    \hline
+    DC Input signal impedance & \multicolumn{4}{c|}{100 k$\Omega$} & Termination off\\
+     & \multicolumn{4}{c|}{50 $\Omega$} & Termination on\\
+    \hline
+    Resolution &\multicolumn{4}{c|}{16 bits}& \\
+    \thickhline
+    \multicolumn{6}{l}{*With the 50\textOmega~termination enabled, the input voltage magnitude must not exceed 5V.}
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+
+The electrical characteristics are based on various test results\footnote{\label{sinara226}https://github.com/sinara-hw/sinara/issues/226}\textsuperscript{,}
+\footnote{\label{sinara489}https://github.com/sinara-hw/sinara/issues/489}\textsuperscript{,}
+\footnote{\label{sampler2}https://github.com/sinara-hw/Sampler/issues/2}.
+
+\begin{table}[hbt!]
+\centering
+\begin{threeparttable}
+\caption{Electrical Characteristics}
+\begin{tabularx}{\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions / Comments} \\
+    \hline
+    % Github wiki page info regarding BW is outdated, so only coarse estimate here
+    % There is an updated plot for this. See the plots.
+    -6dB bandwidth\repeatfootnote{sampler2} & & & & & See bandwidth plots \\
+     & & 200 & & kHz & 1x/10x/100x gain \\
+     & & 90 & & kHz & 1000x gain \\
+    \hline
+    Noise\repeatfootnote{sampler2} & & & & & 83.33 kHz sampling rate \\
+    \hspace{18mm} 1x gain & & 1.78 & & LSB RMS & Termination on \\
+    & & 1.75 & & LSB RMS & Termination off \\
+    \hspace{18mm} 10x gain & & 1.84 & & LSB RMS & Termination on \\
+    & & 3.09 & & LSB RMS & Termination off \\
+    \hspace{18mm} 100x gain & & 3.47 & & LSB RMS & Termination on \\
+    & & 26.02 & & LSB RMS & Termination off \\
+    \hspace{18mm} 1000x gain & & 13.87 & & LSB RMS & Termination on \\
+    & & 206.3 & & LSB RMS & Termination off \\
+    % \hline
+    DC cross-talk\repeatfootnote{sinara226} & & & -96 & dB & 1x gain\\
+    \hline
+    % AC cross-talk data on wiki is also outdated (when it was still novo)
+    % sinara-hw/sinara #489 is a better source of info
+    % But it seems that AC-XT is not channel-invariant
+    % So it is tabulated instead.
+    Second-order harmonics\repeatfootnote{sinara226} & & & & & 25 kHz input, termination on, 1x gain \\
+    & & -51 & & dBc & 0.1 V\textsubscript{pp} (-48dBFS), limited by ADC (-100dBFS) \\
+    & & -69 & & dBc & 1 V\textsubscript{pp} (-28dBFS) \\
+    & & -58.8 & & dBc & 10 V\textsubscript{pp} (-8dBFS) \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Electrical Characteristics (cont.)}
+\begin{tabularx}{\textwidth}{l | c | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Symbol} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions / Comments} \\
+    \hline
+    Common-mode rejection ratio\repeatfootnote{sinara226} & CMRR & & & & & 2 V\textsubscript{pp} sine wave as CM input, termination on\\
+    \hspace{12mm} 1x gain & & & & -98 & dB & $f=0.01,0.1,1$ kHz \\
+    & & & -87 & & dB & $f=10$ kHz \\
+    & & & -55 & & dB & $f=100$ kHz \\
+    & & & -83 & & dB & $f=1$ MHz \\
+    & & & -85 & & dB & $f=10$ MHz \\
+    \cline{3-7}
+    \hspace{12mm} 100x gain & & & & -118 & dB & $f=0.01$ kHz \\
+    & & & -98 & & dB & $f=0.1$ kHz \\
+    & & & -88 & & dB & $f=1$ kHz \\
+    & & & -70 & & dB & $f=10$ kHz \\
+    & & & -50 & & dB & $f=100$ kHz \\
+    & & & -80 & & dB & $f=1$ MHz \\
+    & & & & -118 & dB & $f=10$ MHz \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+Crosstalk between ADC channels of 5108 ADC Sampler is shown below\repeatfootnote{sinara489}.
+
+A 10 V\textsubscript{pp} signal is the input.
+The aggressor channel always has 1x gain.
+All channels have 50 \textOmega~termination enabled.
+
+Data is acquired by taking 512 samples at 80 kHz sampling rate 20 times to average out the FFT.
+
+\newcolumntype{Y}{>{\centering\arraybackslash}X}
+
+\begin{table}[h]
+\begin{threeparttable}
+\caption{Crosstalk with 35 kHz input frequency, 1000x gain on victim}
+\begin{tabularx}{\textwidth}{| c | Y | Y | Y | Y | Y | Y | Y | Y |}
+    \thickhline
+    \multirow{2}{*}{\textbf{Aggressor}} &
+    \multicolumn{8}{c|}{\textbf{Crosstalk (dB) on Victim Channels}}\\
+    \cline{2-9} & 0 & 1 & 2 & 3 & 4 & 5 & 6 & 7 \\
+    \hline
+    Channel 0 & 0.00 &  -114.90 &  -129.35 &  -131.54 &  -132.19 &  -142.56 &  -145.39 &  -159.98 \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[width=\textwidth]{sampler_xt_35khz.png}
+    \caption{Crosstalk with 35 kHz input frequency, 1000x gain on victim, channel 0 as the aggressor}
+\end{figure}
+
+\begin{table}[hbt!]
+\begin{threeparttable}
+\caption{Crosstalk with 300 kHz input frequency, 1000x gain on victim}
+\begin{tabularx}{\textwidth}{| c | Y | Y | Y | Y | Y | Y | Y | Y |}
+    \thickhline
+    \multirow{2}{*}{\textbf{Aggressor}} &
+    \multicolumn{8}{c|}{\textbf{Crosstalk (dB) on Victim Channels}}\\
+    \cline{2-9} & 0 & 1 & 2 & 3 & 4 & 5 & 6 & 7 \\
+    \hline
+    Channel 0 & 0.00 &  -109.18 &  -123.94 &  -128.46 &  -131.11 &  -134.45 &  -135.62 &  -158.51 \\
+    \hline
+    Channel 1 & -112.90 &  0.00 &  -114.98 &  -124.11 &  -131.40 &  -142.61 &  -145.94 &  -168.51 \\
+    \hline
+    Channel 2 & -123.27 &  -112.58 &  0.00 &  -111.17 &  -121.46 &  -129.97 &  -137.31 &  -163.77 \\
+    \hline
+    Channel 3 & -140.61 &  -125.20 &  -114.49 &  0.00 &  -111.84 &  -125.10 &  -133.74 &  -164.55 \\
+    \hline
+    Channel 4 & -140.12 &  -131.07 &  -124.30 &  -112.65 &  0.00 &  -109.22 &  -124.71 &  -160.22 \\
+    \hline
+    Channel 5 & -140.33 &  -135.77 &  -134.42 &  -126.34 &  -116.35 &  0.00 &  -118.40 &  -156.63 \\
+    \hline
+    Channel 6 & -142.39 &  -139.25 &  -138.51 &  -134.73 &  -125.00 &  -108.91 &  0.00 &  -146.29 \\
+    \hline
+    Channel 7 & -145.06 &  -138.97 &  -144.31 &  -139.50 &  -135.50 &  -120.62 &  -114.28 &  0.00 \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+% The plots are quite small given that it is 8-plots-in-1, but the numbers should give a better picture
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[width=\textwidth]{sampler_xt_300khz.png}
+    \caption{Crosstalk with 300 kHz input frequency, 1000x gain on victim, channel 0 as the aggressor}
+\end{figure}
+
+\begin{table}[hbt!]
+\begin{threeparttable}
+\caption{Crosstalk with 300 kHz input frequency, 1x gain on victim}
+\begin{tabularx}{\textwidth}{| c | Y | Y | Y | Y | Y | Y | Y | Y |}
+    \thickhline
+    \multirow{2}{*}{\textbf{Aggressor}} &
+    \multicolumn{8}{c|}{\textbf{Crosstalk (dB) on Victim Channels}}\\
+    \cline{2-9} & 0 & 1 & 2 & 3 & 4 & 5 & 6 & 7 \\
+    \hline
+    Channel 0 & 0.00 & -84.36 & -100.65 & -100.16 & -102.72 & -93.51 & -96.23 & -105.70 \\
+    \hline
+    Channel 1 & -91.95 & 0.00 & -87.47 & -104.87 & -115.80 & -99.91 & -101.55 & -106.71 \\
+    \hline
+    Channel 2 & -109.04 & -86.28 & 0.00 & -88.78 & -96.81 & -95.41 & -108.53 & -109.23 \\
+    \hline
+    Channel 3 & -101.31 & -97.47 & -92.72 & 0.00 & -88.65 & -96.58 & -100.80 & -97.46 \\
+    \hline
+    Channel 4 & -101.27 & -95.18 & -97.16 & -88.29 & 0.00 & -87.26 & -99.11 & -100.12 \\
+    \hline
+    Channel 5 & -103.41 & -102.10 & -101.54 & -104.59 & -99.87 & 0.00 & -89.34 & -102.49 \\
+    \hline
+    Channel 6 & -104.62 & -104.64 & -103.39 & -101.73 & -104.08 & -87.61 & 0.00 & -88.34 \\
+    \hline
+    Channel 7 & -100.67 & -99.20 & -97.34 & -95.48 & -102.93 & -113.76 & -92.80 & 0.00 \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[width=\textwidth]{sampler_xt_300khz_1x_gain.png}
+    \caption{Crosstalk with 300 kHz input frequency, 1x gain on victim, channel 3 as the aggressor}
+\end{figure}
+
+Noise density is measured using the following configuration\repeatfootnote{sampler2}:
+\begin{enumerate}
+    \item 1/12\textmu s sampling rate
+    \item 10k samples per measurement, averaging over 100 measurements
+    \item Measured at channels 6 \& 7. Channel 6 has the 50\textOmega~termination on, channel 7 has it off
+\end{enumerate}
+Noise density with respect to different gain settings with termination on/off are plotted below.
+
+\begin{multicols}{2}
+
+\begin{figure}[H]
+    \includegraphics[width=3.3in]{sampler_noise_term.png}
+    \caption{Noise density with termination enabled}
+\end{figure}
+
+\columnbreak
+
+\begin{figure}[H]
+    \includegraphics[width=3.3in]{sampler_noise_no_term.png}
+    \caption{Noise density with termination disabled}
+\end{figure}
+
+\end{multicols}
+
+\newpage
+
+Bandwidth of small signal and large signal input is shown below\repeatfootnote{sampler2}. The setup is as the following:
+\begin{enumerate}
+    \itemsep0em
+    \item 10k samples, sampled at 79.37 kHz
+    \item Driven by sinusoid from Keysight 33500B generator; Sampled using channel 7 without termination
+    \item Small signal measured using 2V\textsubscript{pp}/gain; Large signal measured using 15V\textsubscript{pp}/gain
+\end{enumerate}
+\begin{multicols}{2}
+
+\begin{figure}[H]
+    \includegraphics[width=3.3in]{sampler_small_signal_bw.png}
+    \caption{Small signal bandwidth}
+\end{figure}
+
+\columnbreak
+
+\begin{figure}[H]
+    \includegraphics[width=3.3in]{sampler_large_signal_bw.png}
+    \caption{Large signal bandwidth}
+\end{figure}
+
+\end{multicols}
+
+\newpage
+
+\section{Front Panel Drawings}
+\begin{multicols}{2}
+
+\begin{center}
+    \centering
+    \includegraphics[height=2.7in]{sampler_drawings.pdf}
+    \captionof{figure}{5108 ADC Sampler front panel drawings}
+\end{center}
+
+\columnbreak
+
+\begin{center}
+    \centering
+    \includegraphics[height=2.7in]{sampler_assembly.pdf}
+    \captionof{figure}{5108 ADC Sampler front panel assembly}
+\end{center}
+
+\end{multicols}
+
+\begin{multicols}{2}
+\begin{center}
+    \captionof{table}{Bill of Material (Standalone)}
+    \tiny
+    \begin{tabular}{|c|c|c|c|}
+    \hline
+    Index & Part No. & Qty & Description \\ \hline
+    1 & 90504202 & 1 & FP-FRONT PANEL, EXTRUDED, TYPE 2, STATIC, 3Ux8HP \\ \hline
+    2 & 3218843 & 2 & FP-ALIGNMENT PIN (LOCALIZATION) \\ \hline
+    3 & 3020716 & 0.04 & SLEEVE GREY PLAS.M2.5 (100PCS) \\ \hline
+    \end{tabular}
+\end{center}
+\columnbreak
+\begin{center}
+    \captionof{table}{Bill of Material (Assembled)}
+    \tiny
+    \begin{tabular}{|c|c|c|c|}
+    \hline
+    Index & Part No. & Qty & Description \\ \hline
+    1 & 90504202 & 1 & FP-LYKJ 3U4HP PANEL \\ \hline
+    2 & 3033098 & 0.04 & SCREW COLLAR M2.5X12.3 (100X) \\ \hline
+    3 & 3040138 & 2 & PB HOLDER DIE-CAST \\ \hline
+    4 & 3001012 & 2 & SCR M2.5*6 PAN PHL NI DIN7985 \\ \hline
+    5 & 3010110 & 0.02 & WASHER PLN.M2.7 DIN125 (100X) \\ \hline
+    6 & 3201099 & 0.01 & SCR M2.5*8 OVL PHL ST NI 100EA \\ \hline
+    7 & 3040005 & 1 & HANDLE 8HP GREY PLASTIC \\ \hline
+    8 & 3207076 & 0.01 & SCR M2.5*12 PAN 100 21101-222 \\ \hline
+    9 & 3201130 & 0.01 & NUT M2.5 HEX ST NI KIT (100PCS) \\ \hline
+    10 & 3211232 & 1 & SCR M2.5*14 PAN PHL SS \\ \hline
+    \end{tabular}
+\end{center}
+\end{multicols}
+
+\section{Configuring Termination}
+\begin{multicols}{2}
+The input termination can be configured by switches.
+The per-channel termination switches are found at the middle left part of the card.
+
+Switching on the termination switch adds a 50\textOmega~termination between the differential input signals.
+
+Regardless of the switch configurations, the differential input signals are separately terminated with 100k\textOmega~to the PCB ground.
+\columnbreak
+\begin{center}
+    \centering
+    \includegraphics[height=1.7in]{sampler_switches.jpg}
+    \captionof{figure}{Position of switches}
+\end{center}
+\end{multicols}
+
+\newpage
+
+\section{Example ARTIQ code}
+The sections below demonstrate simple usage scenarios of the 5108 ADC Sampler card with the ARTIQ control system.
+They do not exhaustively demonstrate all the features of the ARTIQ system.
+The full documentation for the ARTIQ software and gateware is available at \url{https://m-labs.hk}.
+
+\subsection{Get input voltage}
+The following example initializes the Sampler card with 1x gain on all ADC channels.
+Sample all ADC channels at the end.
+
+\inputcolorboxminted{firstline=9,lastline=21}{examples/sampler.py}
+
+\subsection{Voltage-controlled DDS Amplitude (SU-Servo Only)}
+The SU-Servo feature can be enabled by integrating the 5108 ADC Sampler with 4410 DDS Urukuls.
+Amplitude of the DDS output can be controlled by the ADC input of the Sampler through PI control, characterised by the following transfer function.
+\[H(s)=k_p+\frac{k_i}{s+\frac{k_i}{g}}\]
+In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.
+First, initialize the RTIO, SU-Servo and its channel with 1x gain.
+
+\inputcolorboxminted{firstline=10,lastline=17}{examples/suservo.py}
+
+Next, setup the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
+
+\inputcolorboxminted{firstline=18,lastline=25}{examples/suservo.py}
+
+Then, configure the DDS frequency to 10 MHz with 3V input offset.
+When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
+
+\inputcolorboxminted{firstline=26,lastline=30}{examples/suservo.py}
+
+SU-Servo encodes the ADC voltage in a linear scale [-1, 1].
+Therefore, 3V is converted to 0.3.
+Note that the ASF of all DDS channels are capped at 1.0, the amplitude clips when ADC input $\leq -7V$ with the above IIR filter.
+
+Finally, enable the SU-Servo channel with the IIR filter programmed beforehand.
+
+\inputcolorboxminted{firstline=32,lastline=33}{examples/suservo.py}
+
+A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC.
+The RMS voltage of the DDS channel against the ADC voltage is plotted.
+The DDS channel is terminated with 50\textOmega.
+
+\begin{center}
+\begin{tikzpicture}[
+    declare function={
+        func(\x)= and(\x>=-10, \x<-7) * (160) +
+            and(\x>=-7, \x<3) * (16*(3-x)) +
+            and(\x>=3, \x<10) * (0);
+    }
+]
+\begin{axis}[
+    axis x line=middle, axis y line=middle,
+    every axis x label/.style={
+        at={(axis description cs:0.5,-0.1)},
+        anchor=north,
+    },
+    every axis y label/.style={
+        at={(ticklabel* cs:1.05)},
+        anchor=south,
+    },
+    minor x tick num=3,
+    grid=both,
+    height=8cm,
+    width=12cm,
+    ymin=-5, ymax=180, ytick={0,16,...,160}, ylabel=DDS RMS Voltage ($mV_{rms}$),
+    xmin=-10, xmax=10, xtick={-10,-8,...,10}, xlabel=Sampler Voltage ($V$),
+]
+
+\addplot[very thick, blue, samples=21, domain=-10:10]{func(x)};
+\end{axis}
+\end{tikzpicture}
+\end{center}
+
+DDS signal should be attenuated.
+High output power affects the linearity due to the 1 dB compression point of the amplifier at 13 dBm output power.
+15 dB attenuation at the digital attenuator was applied in this example.
+
+\section{Ordering Information}
+To order, please visit \url{https://m-labs.hk} and select the 5108 ADC Sampler in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
+
+\section*{}
+\vspace*{\fill}
+
+\input{footnote.tex}
+
+\end{document}

5432.tex

@@ -0,0 +1,249 @@
+\input{preamble.tex}
+\graphicspath{{images/5432}{images}}
+
+\title{5432 DAC Zotino}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 2}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{32-channel DAC}
+\item{16-bits resolution}
+\item{1 MSPS shared between all channels}
+\item{Output voltage $\pm$10V}
+\item{HD68 connector}
+\item{Can be broken out to BNC/SMA/MCX}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{Controlling setpoints of PID controllers for laser power stabilization}
+\item{Low-frequency arbitrary waveform generation}
+\item{Driving DC electrodes in ion traps}
+\end{itemize}
+
+\section{General Description}
+The 5432 Zotino is a 4hp EEM module and part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
+
+It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.88}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        % HD68 Connector
+        \draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
+
+        % IDC Connectors to IDC cards
+        \draw (2.2, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem2) {};
+        \draw (1.4, 1.2) node[twoportshape, t={\twocm{IDC}{DAC 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem3) {};
+        \draw (2.2, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem1) {};
+        \draw (1.4, -1.2) node[twoportshape, t={\twocm{IDC}{DAC 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (eem0) {};
+
+        % Op-amp x32
+        \draw (3, 0) node[buffer, circuitikz/bipoles/twoport/width=1.2, scale=-0.5] (amp) {};
+
+        % DAC AD5372
+        \draw (4.6, 0.2) node[twoportshape, t=\twocm{32-CH}{DAC}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (dac) {};
+
+        % LVDS Transceivers
+        \draw (6.6, 0) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds0) {};
+        \draw (6.6, -1.6) node[twoportshape, t=\fourcm{LVDS}{Transceiever}, circuitikz/bipoles/twoport/width=1.8, scale=0.5, rotate=-90] (lvds1) {};
+
+        % Aesthetic EEPROM
+        \draw (6.6, 1.6) node[twoportshape, t={EEPROM}, circuitikz/bipoles/twoport/width=1.6, scale=0.5, rotate=-90] (eeprom) {};
+
+        % EEMs from core device / controllers
+        \draw (8.2, 0.0) node[twoportshape, t={EEM Port}, circuitikz/bipoles/twoport/width=3.6, scale=0.7, rotate=-90] (eem_in) {};
+
+        % Connect EEM IN to LVDS & EEMPROM
+        \draw [latexslim-latexslim] (eeprom.north) -- (7.85, 1.6);
+        \draw [latexslim-latexslim] (lvds0.north) -- (7.85, 0);
+        \draw [latexslim-latexslim] (lvds1.north) -- (7.85, -1.6);
+
+        % Connect LVDS to DAC
+        \draw [latexslim-latexslim] (lvds0.south) -- (5.2, 0);
+        \draw [latexslim-latexslim] (lvds1.south) -- (4.6, -1.6) -- (dac.south);
+
+        % Connect DAC to Op-amp, label op-amp width x32
+        \draw [-latexslim] (4, 0) -- (amp.west);
+        \node [label=below:\tiny{Op-amp x32}] at (3.2, -0.2) {};
+        \node [label=below:\tiny{1 per ch.}] at (3.2, -0.45) {};
+
+        % Connect Op-amp to EEM OUT and HD68
+        \draw [-latexslim] (amp.east) -- (hd68.east);
+        \draw [-latexslim] (2.2, 0) -- (eem2.east);
+        \draw [-latexslim] (1.4, 0) -- (eem3.east);
+        \draw [-latexslim] (2.2, 0) -- (eem1.west);
+        \draw [-latexslim] (1.4, 0) -- (eem0.west);
+
+        % TEC Cooler on top of the DAC
+        % To make it more obvious that it is cooling the DAC
+        \draw (4.6, 1.45) node[twoportshape, t=\fourcm{TEC}{Cooler}, circuitikz/bipoles/twoport/width=1.2, circuitikz/bipoles/twoport/height=1.2, scale=0.7] (tec_cooler) {};
+
+        % TEC Controller lined up with EEM IN
+        \draw (8.2, 3.5) node[twoportshape, t=\fourcm{TEC Controller}{Connector}, circuitikz/bipoles/twoport/width=2.6, scale=0.7, rotate=-90] (tec_conn) {};
+
+        % Thermistor for TEC controller
+        \draw (6.6, 3.3) node[thermistorshape, scale=0.7, rotate=-90] (thermistor) {};
+        \draw [latexslim-] (7.85, 3.3) -- (6.75, 3.3);
+
+        % Connect the controller to the cooler
+        \draw [-latexslim] (7.85, 4.2) -- (4.6, 4.2) -- (tec_cooler.north);
+
+        % Thermal connection between DAC and thermistor
+        \draw [densely dotted] (thermistor.south) -- (5.6, 3.3) -- (5.6, 0.5) -- (5.2, 0.5);
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2in]{photo5432.jpg}
+    \caption{Zotino card photograph}
+\end{figure}
+
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2.3in, angle=90]{Zotino_FP.jpg}
+    \caption{Zotino front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{5432 DAC Zotino}{https://github.com/sinara-hw/Zotino/}
+
+\section{Electrical Specifications}
+
+% \hypersetup{hidelinks}
+% \urlstyle{same}
+These specifications are based on the datasheet of the DAC IC
+(AD5372BCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
+and various information from the Sinara wiki\footnote{\label{zotino_wiki}\url{https://github.com/sinara-hw/Zotino/wiki}}.
+
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Output Specifications}
+\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Output voltage & -10 & & 10 & V & \\
+    \hline
+    Output impedance\repeatfootnote{zotino_wiki} & \multicolumn{4}{c|}{470 $\Omega$ $||$ 2.2nF} & \\
+    \hline
+    Resolution\repeatfootnote{dac} & & 16 & & bits & \\
+    \hline
+    3dB bandwidth\repeatfootnote{zotino_wiki} & & 75 & & kHz & \\
+    \hline
+    Power consumption\repeatfootnote{zotino_wiki} & 3 & & 8.7 & W & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+The following table records the cross-talk and transient behavior of Zotino\footnote{\label{zotino21}\url{https://github.com/sinara-hw/Zotino/issues/21}}. In terms of output noise, measurements were made after a 15-cm IDC cable, IDC-SMA, 100 cm coax ($\sim$50 pF), and 500 k$\Omega$ $||$ 150 pF\footnote{\label{zotino27}\url{https://github.com/sinara-hw/Zotino/issues/27}}. DAC output during noise measurement was 3.5 V.
+
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Electrical Characteristics}
+\begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions / Comments} \\
+    \hline
+    DC cross-talk\repeatfootnote{zotino21}  & & -116 & & dB & \\
+    \hline
+    Fall-time\repeatfootnote{zotino21}  & & 18.5 & & $\mu$s & 10\% to 90\% fall-time \\
+    & & 25 & & $\mu$s & 1\% to 99\% fall-time \\
+    \hline
+    Negative overshoot\repeatfootnote{zotino21}  & & 0.5\% & & - & \\
+    \hline
+    Rise-time\repeatfootnote{zotino21}  & & 30 & & $\mu$s & 1\% to 99\% rise-time \\
+    \hline
+    Positive overshoot\repeatfootnote{zotino21} & & 0.65\% & & - & \\
+    \hline
+    Output noise\repeatfootnote{zotino27} & & & & & \\
+    \hspace{18mm} @ 100 Hz & & 500 & & nV/rtHz & 6.9 Hz bandwidth \\
+    \hspace{18mm} @ 300 Hz & & 300 & & nV/rtHz & 6.9 Hz bandwidth \\
+    \hspace{18mm} @ 50 kHz & & 210 & & nV/rtHz & 6.9 kHz bandwidth \\
+    \hspace{18mm} @ 1 MHz & & 4.6 & & nV/rtHz & 6.9 kHz bandwidth \\
+    \hspace{18mm} $>$ 4 MHz & & & 1 & nV/rtHz & 6.9 kHz bandwidth \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\newpage
+
+Step response was found by setting the DAC register to 0x0000 (-10V) or 0xFFFF (10V) and observing the waveform\repeatfootnote{zotino21}.
+
+\begin{figure}[hbt!]
+    \centering
+    \subfloat[\centering Switching from -10V to +10V]{{
+        \includegraphics[height=1.8in]{zotino_step_response_rising.png}
+    }}%
+    \subfloat[\centering Switching from +10V to -10V]{{
+        \includegraphics[height=1.8in]{zotino_step_response_falling.png}
+    }}%
+    \caption{Step response}%
+\end{figure}
+
+Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21}:
+
+\begin{enumerate}
+    \item CH1 as aggressor, CH0 as victim
+    \item CH0, 2-7 terminated, CH 8-31 open
+    \item Aggressor signal from BNC passed through 15cm IDC26, 2m HD68-HD68 SCSI-3 shielded twisted pair, 15cm IDC26, converted back to BNC with adapters between all different cables and connectors.
+\end{enumerate}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[width=3.3in]{zotino_fext.png}
+    \caption{Step crosstalk}
+\end{figure}
+
+\newpage
+
+\codesection{5432 DAC Zotino}
+
+\subsection{Setting output voltage}
+The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
+
+\inputcolorboxminted{firstline=11,lastline=22}{examples/zotino.py}
+
+\newpage
+
+\subsection{Triangular wave}
+Generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
+
+Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
+
+\inputcolorboxminted{firstline=30,lastline=49}{examples/zotino.py}
+
+\ordersection{5432 DAC Zotino}
+
+\finalfootnote
+
+\end{document}

5518-5528.tex

@@ -0,0 +1,246 @@
+\input{preamble.tex}
+\graphicspath{{images/5518-5528}{images}}
+
+\title{5518 BNC-IDC / 5528 SMA-IDC}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+    \item{8 channels}
+    \item{Internal IDC connector}
+    \item{External BNC or SMA connectors}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+    \item{Break out analog signals}
+    \item{BNC or SMA adapters for: \begin{itemize}
+        \item{5432 DAC Zotino}
+        \item{5632 DAC Fastino}
+    \end{itemize}}
+    \item{(5528 only) SMA adapter for 5108 Sampler}
+    \item{Convert from/to HD68 with 5568 HD68-IDC}
+\end{itemize}
+
+\section{General Description}
+The 5518 BNC-IDC card is a 8hp EEM module; the 5528 SMA-IDC card is a 4hp EEM module. Both adapter cards break out analog signals from IDC connectors to BNC (5518) or SMA (5528). IDC connectors can be found on 5108 Sampler, 5432 DAC Zotino, 5632 DAC Fastino and 5568 HD68-IDC.
+
+Each card provides 8 channels, with respectively BNC or SMA connectors. Breaking out all 32 channels of 5432 DAC Zotino, 5632 DAC Fastino or 5568 HD68-IDC requires four BNC/SMA-IDC cards. Breaking out all 8 ADC channels of 5108 Sampler requires only one BNC/SMA-IDC card.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.95}{
+    \begin{circuitikz}[european, scale=1.2, every label/.append style={align=center}]
+
+        \begin{scope}[]
+
+            % Node to pin-point the locations of IO symbols
+            \draw[color=white, text=black] (-0.1,  2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io0) {};
+            \draw[color=white, text=black] (-0.1,  1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io1) {};
+            \draw[color=white, text=black] (-0.1,  1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io2) {};
+            \draw[color=white, text=black] (-0.1,  0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io3) {};
+            \draw[color=white, text=black] (-0.1, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io4) {};
+            \draw[color=white, text=black] (-0.1, -1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io5) {};
+            \draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io6) {};
+            \draw[color=white, text=black] (-0.1, -2.45) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (io7) {};
+
+            % Labels for all IO symbols
+            \node [label=left:\tiny{IO 0}] at (0.25,  2.45) {};
+            \node [label=left:\tiny{IO 1}] at (0.25,  1.75) {};
+            \node [label=left:\tiny{IO 2}] at (0.25,  1.05) {};
+            \node [label=left:\tiny{IO 3}] at (0.25,  0.35) {};
+            \node [label=left:\tiny{IO 4}] at (0.25, -0.35) {};
+            \node [label=left:\tiny{IO 5}] at (0.25, -1.05) {};
+            \node [label=left:\tiny{IO 6}] at (0.25, -1.75) {};
+            \node [label=left:\tiny{IO 7}] at (0.25, -2.45) {};
+
+            % draw all IO symbols
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=35cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=15cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=5cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-5cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-15cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-25cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-35cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+
+            % Draw CH0, CH1 & CH7 CM chokes
+            \draw (3,  1.2) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm0) {};
+            \draw (3,  0.4) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm1) {};
+            \draw (3, -1.1) node[twoportshape, t=\fourcm{Common Mode}{Line Filter}, circuitikz/bipoles/twoport/width=2.2, scale=0.6] (cm7) {};
+
+            % Omission dots for other channels
+            \node at (3, -0.15)[circle,fill,inner sep=0.7pt]{};
+            \node at (3, -0.35)[circle,fill,inner sep=0.7pt]{};
+            \node at (3, -0.55)[circle,fill,inner sep=0.7pt]{};
+
+            % IDC26 connector
+            \draw (5.13, 0) node[twoportshape, t={IDC Port}, circuitikz/bipoles/twoport/width=3.8, scale=0.7, rotate=-90] (idc) {};
+
+            % Connect IO connectors to CM chokes
+            \draw [latexslim-latexslim] (io0.east) -- (1.3,  2.45) -- (1.3,  1.2) -- (cm0.west);
+            \draw [latexslim-latexslim] (io1.east) -- (1.2,  1.75) -- (1.2,  0.4) -- (cm1.west);
+            \draw [latexslim-latexslim] (io2.east) -- (1.1,  1.05) -- (1.1, -0.15) -- (2.5, -0.15);
+            \draw [latexslim-latexslim] (io3.east) -- (1.0,  0.35) -- (1.0, -0.25) -- (2.5, -0.25);
+            \draw [latexslim-latexslim] (io4.east) -- (1.0, -0.35) -- (1.0, -0.35) -- (2.5, -0.35);
+            \draw [latexslim-latexslim] (io5.east) -- (1.1, -1.05) -- (1.1, -0.45) -- (2.5, -0.45);
+            \draw [latexslim-latexslim] (io6.east) -- (1.2, -1.75) -- (1.2, -0.55) -- (2.5, -0.55);
+            \draw [latexslim-latexslim] (io7.east) -- (1.3, -2.45) -- (1.3, -1.1) -- (cm7.west);
+
+            % Connect CM chokes to the IDC connector
+            \draw [latexslim-latexslim] (cm0.east) -- (4.85,  1.2);
+            \draw [latexslim-latexslim] (cm1.east) -- (4.85,  0.4);
+            \draw [latexslim-latexslim] (3.5, -0.15) -- ++(1.35, 0);
+            \draw [latexslim-latexslim] (3.5, -0.25) -- ++(1.35, 0);
+            \draw [latexslim-latexslim] (3.5, -0.35) -- ++(1.35, 0);
+            \draw [latexslim-latexslim] (3.5, -0.45) -- ++(1.35, 0);
+            \draw [latexslim-latexslim] (3.5, -0.55) -- ++(1.35, 0);
+            \draw [latexslim-latexslim] (cm7.east) -- (4.85, -1.1);
+
+        \end{scope}
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \subfloat[\centering BNC-IDC]{{
+        \includegraphics[height=2.5in]{photo5518.jpg}
+    }}%
+    \subfloat[\centering SMA-IDC]{{
+        \includegraphics[height=2.6in]{photo5528.jpg}
+    }}%
+    \caption{BNC-IDC/SMA-IDC card photos}%
+    \label{fig:example}%
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesectiond{5518 BNC-IDC}{5528 SMA-IDC}{https://github.com/sinara-hw/BNC\_IDC}{https://github.com/sinara-hw/SMA\_IDC\_Adapter}
+
+\section{Electrical Specifications}
+
+Specifications of parameters are based on the datasheet of the
+common mode line filter\footnote{\label{cm_choke}\url{https://www.we-online.com/catalog/datasheet/744229.pdf}}.
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Electrical Specifications}
+\begin{tabularx}{0.65\textwidth}{l | c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Max. Value} & \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Rated voltage & 80 & V & \\
+    \hline
+    Rated current & 400 & mA & $\Delta T^{*}=40K$ \\
+    \thickhline
+\end{tabularx}
+*$\Delta T$ refers to the temperature of the CM line filter minus the ambient.
+\end{threeparttable}
+\end{table}
+
+Impedance characteristics of common mode \& differential mode signal at different frequencies are shown in the following graph:
+
+\begin{figure}[H]
+    \centering
+    \includegraphics[height=4.8in]{idc_cm_choke.jpg}
+    \caption{Common Mode Line Filter Impedance Characteristics}
+\end{figure}
+
+\newpage
+
+\section{Channel Mapping}
+The following table shows the corresponding channel numbers of the BNC/SMA-IDC adapter IO ports when connected to Sinara cards that support IDC connections.
+\begin{table}[h]
+    \caption{Channel Mapping of BNC/SMA-IDC to Zotino, Fastino \& HD68-IDC}
+    \centering
+    \begin{tabular}{|c|c|c|c|c|c|c|c|c|}
+    \hline
+    IDC Port Label & \multicolumn{1}{l|}{IO 0} & \multicolumn{1}{l|}{IO 1} & \multicolumn{1}{l|}{IO 2} & \multicolumn{1}{l|}{IO 3} & \multicolumn{1}{l|}{IO 4} & \multicolumn{1}{l|}{IO 5} & \multicolumn{1}{l|}{IO 6} & \multicolumn{1}{l|}{IO 7} \\ \hline
+    CH 0-7         & 0                         & 1                         & 2                         & 3                         & 4                         & 5                         & 6                         & 7                         \\ \hline
+    CH 8-15        & 8                         & 9                         & 10                        & 11                        & 12                        & 13                        & 14                        & 15                        \\ \hline
+    CH 16-23       & 16                        & 17                        & 18                        & 19                        & 20                        & 21                        & 22                        & 23                        \\ \hline
+    CH 24-31       & 24                        & 25                        & 26                        & 27                        & 28                        & 29                        & 30                        & 31                        \\ \hline
+    \end{tabular}
+\end{table}
+
+\begin{table}[h]
+    \caption{Channel Mapping of BNC/SMA-IDC to 5108 Sampler}
+    \centering
+    \begin{tabular}{|l|l|l|l|l|l|l|l|l|}
+    \hline
+                    & IO 0              & IO 1                   & IO 2                   & IO 3                   & IO 4                   & IO 5                   & IO 6                   & IO 7                   \\ \hline
+    Sampler Ch. & \multicolumn{1}{c|}{7} & \multicolumn{1}{c|}{6} & \multicolumn{1}{c|}{5} & \multicolumn{1}{c|}{4} & \multicolumn{1}{c|}{3} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{0} \\ \hline
+    \end{tabular}
+\end{table}
+
+\ordersection{5518 BNC-IDC/5528 SMA-IDC}
+
+\finalfootnote
+
+
+\end{document}

5568.tex

@@ -0,0 +1,97 @@
+\input{preamble.tex}
+\graphicspath{{images/5568}{images}}
+
+\title{5568 HD68-IDC}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+    \item{32 channels}
+    \item{Internal IDC connector}
+    \item{External HD68 connectors}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+    \item{Branch out analog signal from: \begin{itemize}
+        \item{5432 DAC Zotino}
+        \item{5632 DAC Fastino}
+    \end{itemize}}
+    \item{BNC or SMA adapter when used with: \begin{itemize}
+        \item{5518 BNC-IDC}
+        \item{5528 SMA-IDC}
+    \end{itemize}}
+\end{itemize}
+
+\section{General Description}
+The 5568 HD68-IDC card is a 4hp EEM module, part of the ARTIQ/Sinara family. It is an adapter card that converts IDC connections to or from HD68 connections. It can be connected via external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
+
+Each card supports 32 channels, with one HD68 connector and four IDC connectors. Each IDC connector supports 8 channels. All 32 channels can be accessed using an external HD68 cable.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{1}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        % HD68 Connector
+        \draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
+
+        % IDC Connectors to IDC cards
+        \draw (3.0, 1.8) node[twoportshape, t={\twocm{IDC}{CH 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem2) {};
+        \draw (1.8, 1.8) node[twoportshape, t={\twocm{IDC}{CH 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem3) {};
+        \draw (3.0, -1.8) node[twoportshape, t={\twocm{IDC}{CH 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem1) {};
+        \draw (1.8, -1.8) node[twoportshape, t={\twocm{IDC}{CH 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem0) {};
+
+        % Connect Op-amp to EEM OUT and HD68
+        \draw [-latexslim] (3.0, 0) -- (hd68.east);
+        \draw [-latexslim] (3.0, 0) -- (eem2.east);
+        \draw [-latexslim] (1.8, 0) -- (eem3.east);
+        \draw [-latexslim] (3.0, 0) -- (eem1.west);
+        \draw [-latexslim] (1.8, 0) -- (eem0.west);
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[h]
+    \centering
+    \includegraphics[height=3.5in, angle=90]{photo5568.jpg}
+    \includegraphics[height=3in, angle=90]{HD68_IDC_FP.pdf}
+    \caption{Card and front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{5568 HD68-IDC}{https://github.com/sinara-hw/IDC_HD68_Adapter}
+
+\section{Cable Connection Diagram}
+The 5568 HD68-IDC card can convert signals from HD68 format to IDC format. Within the Sinara family, the analog output of 5432 DAC Zotino \& 5632 DAC Fastino cards is exported using HD68 connectors. To break out the analog signal into a different crate, connect 5568 HD68-IDC with the DAC card using an external SCSI cable. Then plug in IDC cables to the appropriate IDC connectors to break out the signal to e.g. 5518 BNC-IDC, 5528 SMA-IDC, or 5538 MCX-IDC.
+
+The cable connections for 5568 HD68-IDC can be seen in the diagram below.
+
+\begin{figure}[h]
+    \centering
+    \includegraphics[height=4in]{hd68_idc_connection.pdf}
+    \caption{HD68-IDC connection diagram}
+\end{figure}
+
+\ordersection{5568 HD68-IDC}
+
+\finalfootnote
+
+\end{document}

7210.tex

@@ -0,0 +1,299 @@
+\input{preamble.tex}
+\graphicspath{{images/7210}{images}}
+
+\title{7210 Clocker}
+\author{M-Labs Limited}
+\date{January 2024}
+\revision{Revision 3}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{Low-jitter clock signal distribution}
+\item{SMA \& MMCX input}
+\item{4 SMA \& 6 MMCX output}
+\item{\textless100 fs RMS jitter}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+    \item{Distribute clock signals}
+    \item{Amplify clock signals}
+    \item{Drive clock input for:\begin{itemize}
+        \item{4410/4412 DDS Urukul}
+        \item{4456 Synthesizer Mirny}
+        \item{4624 Phaser}
+    \end{itemize}}
+\end{itemize}
+
+\section{General Description}
+The 7210 Clocker card is a 4hp EEM module, capable of distributing clock signals with \textless100 fs RMS jitter.
+
+Clock input can be supplied to Clocker through the external SMA connector or the internal MMCX connector. The input source is selected using an SPDT switch.
+
+Each Clocker card distributes an input to 10 outputs. 4 outputs are interfaced with SMA connectors, the other 6 with MMCX connectors.
+
+Clocker can be powered externally or internally. To provide external power, connect an external 12V power source either through front panel power jack or rear connector. Alternatively, connect it to a carrier card (e.g. 1124 Kasli, 1125 Kasli-SoC) using the EEM port.
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{0.95}{
+    \begin{circuitikz}[european, scale=1.2, every label/.append style={align=center}]
+
+        \begin{scope}[]
+
+            % Node to pin-point the locations of IO symbols
+            \draw[color=white, text=black] (-0.1,  1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma1) {};
+            \draw[color=white, text=black] (-0.1,  1.4) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma0) {};
+            \draw[color=white, text=black] (-0.1,  0.7) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma2) {};
+            \draw[color=white, text=black] (-0.1,  0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma3) {};
+            \draw[color=white, text=black] (-0.1, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx4) {};
+            \draw[color=white, text=black] (-0.1, -0.7) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx5) {};
+            \draw[color=white, text=black] (-0.1, -1.05) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx6) {};
+            \draw[color=white, text=black] (-0.1, -1.4) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx7) {};
+            \draw[color=white, text=black] (-0.1, -1.75) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx8) {};
+            \draw[color=white, text=black] (-0.1, -2.1) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx9) {};
+
+            % Labels for all IO symbols
+            \node [label=center:\tiny{OUT 0}] at (sma0) {};
+            \node [label=center:\tiny{OUT 1}] at (sma1) {};
+            \node [label=center:\tiny{OUT 2}] at (sma2) {};
+            \node [label=center:\tiny{OUT 3}] at (sma3) {};
+            \node [label=center:\tiny{OUT 4}] at (mmcx4) {};
+            \node [label=center:\tiny{OUT 5}] at (mmcx5) {};
+            \node [label=center:\tiny{OUT 6}] at (mmcx6) {};
+            \node [label=center:\tiny{OUT 7}] at (mmcx7) {};
+            \node [label=center:\tiny{OUT 8}] at (mmcx8) {};
+            \node [label=center:\tiny{OUT 9}] at (mmcx9) {};
+
+            % draw all IO symbols
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-20cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-15cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-10cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=-5cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=5cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=10cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=15cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=20cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=25cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=-90, xshift=30cm, yshift=2cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+
+            % Draw dotted enclosure to diferentiate SMA from MMCX outputs
+            % Extend the enclosure to the right
+            \draw[color=white, text=black] (0.5, 0.35) node[twoportshape, circuitikz/bipoles/twoport/width=0.1, scale=0.1 ] (sma_east) {};
+            \draw[color=white, text=black] (0.5, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=0.1, scale=0.1 ] (mmcx_east) {};
+            \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(sma0) (sma3.south west) (sma_east)] (sma_box) {};
+            \node[fill=white, rotate=-90] at (sma_box.west) {SMA};
+            \node[draw, dotted, thick, rounded corners, inner xsep=0.7em, inner ysep=0.4em, fit=(mmcx9) (mmcx4.north west) (mmcx_east)] (mmcx_box) {};
+            \node[fill=white, rotate=-90] at (mmcx_box.west) {MMCX};
+
+            % Draw clock buffer
+            \draw (2.6, 0) node[twoportshape, t={Clock Buffer}, circuitikz/bipoles/twoport/width=2, circuitikz/bipoles/twoport/height=2, scale=0.7] (clk_buf) {};
+
+            % Draw clock input symbols
+            \begin{scope}[scale=0.07 , rotate=90, xshift=-5cm, yshift=-66cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \begin{scope}[scale=0.07 , rotate=90, xshift=5cm, yshift=-66cm]
+                \draw (0,0.65) -- (0,3);
+                \clip (-1.5,0) rectangle (1.5,1.5);
+                \draw (0,0) circle(1.5);
+                \clip (-0.8,0) rectangle (0.8,0.8);
+                \draw (0,0) circle(0.8);
+            \end{scope}
+            \draw[color=white, text=black] (4.5,  0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (mmcx_clkin) {};
+            \draw[color=white, text=black] (4.5, -0.35) node[twoportshape, circuitikz/bipoles/twoport/width=1.2, scale=0.4 ] (sma_clkin) {};
+            \node [label=right:\tiny{MMCX CLK IN}] at (mmcx_clkin) {};
+            \node [label=right:\tiny{SMA CLK IN}] at  (sma_clkin) {};
+
+            % Draw the SPDT switch
+            \draw (2.6, -2) node[twoportshape,t=\fourcm{Input Clock \phantom{spac} }{Selection Switch}, circuitikz/bipoles/twoport/width=2.7, scale=0.6] (clk_sel) {};
+            \begin{scope}[xshift=3cm, yshift=-1.78cm, scale=0.12, every node/.style={scale=0.1}, rotate=-90 ]
+                \draw (0.4,0) to[short,-o](0.75,0);
+                \draw (0.78,0)-- +(30:0.46);
+                \draw (1.25,0)to[short,o-](1.6,0);
+            \end{scope}
+
+            % Connect CLKINs to the clock buffer
+            \draw [-latexslim] (4.41,  0.35) -- (3.41, 0.35);
+            \draw [-latexslim] (4.41, -0.35) -- (3.41, -0.35);
+
+            % Connect the CLK SEL switch to the clock buffer
+            \draw [-latexslim] (clk_sel.north) -- (clk_buf.south);
+
+            % Connect the clock buffer to all output connectors
+            \draw [-latexslim] (1.79, 0.2) -- (1, 0.2) -- (1, 0.35) -- (0.25, 0.35);
+            \draw [-latexslim] (1.79, 0.3) -- (1.1, 0.3) -- (1.1, 0.7) -- (0.25, 0.7);
+            \draw [-latexslim] (1.79, 0.4) -- (1.2, 0.4) -- (1.2, 1.05) -- (0.25, 1.05);
+            \draw [-latexslim] (1.79, 0.5) -- (1.3, 0.5) -- (1.3, 1.4) -- (0.25, 1.4);
+
+            \draw [-latexslim] (1.79, -0.1) -- (0.9, -0.1) -- (0.9, -0.35) -- (0.25, -0.35);
+            \draw [-latexslim] (1.79, -0.2) -- (1.0, -0.2) -- (1.0,  -0.7) -- (0.25, -0.7);
+            \draw [-latexslim] (1.79, -0.3) -- (1.1, -0.3) -- (1.1, -1.05) -- (0.25, -1.05);
+            \draw [-latexslim] (1.79, -0.4) -- (1.2, -0.4) -- (1.2,  -1.4) -- (0.25, -1.4);
+            \draw [-latexslim] (1.79, -0.5) -- (1.3, -0.5) -- (1.3, -1.75) -- (0.25, -1.75);
+            \draw [-latexslim] (1.79, -0.6) -- (1.4, -0.6) -- (1.4,  -2.1) -- (0.25, -2.1);
+
+        \end{scope}
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\vspace{5mm}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=3.5in]{photo7210.jpg}
+    \includegraphics[height=3.5in]{clocker_front_panel.jpg}
+    \caption{Clocker card and front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{7210 Clocker}{https://github.com/sinara-hw/Clocker}
+
+\section{Electrical Specifications}
+
+Specifications are derived based on the datasheets of the clock buffer (ADCLK950BCPZ\footnote{\url{https://www.analog.com/media/en/technical-documentation/data-sheets/ADCLK950.pdf}}) and the RF transformer (TCM2-43X+\footnote{\url{https://www.minicircuits.com/pdfs/TCM2-43X+.pdf}}) used. Clock output specifications are tested by supplying a 100 MHz DDS signal to the SMA input connector\footnote{\label{clocker6}\url{https://github.com/sinara-hw/Clocker/issues/6\#issuecomment-414048168}}. The output is connected to an oscilloscope with 50\textOmega~termination.
+
+\begin{table}[h]
+\centering
+\begin{threeparttable}
+\caption{Clock Specifications}
+\begin{tabularx}{0.9\textwidth}{l | c c c | c | X}
+    \thickhline
+    \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+    \textbf{Unit} & \textbf{Conditions} \\
+    \hline
+    Clock input & & & & & \\
+            \hspace{3mm} Peak-to-peak voltage & 0.40 & & 2.40 & V\textsubscript{p-p} & \\
+            \hspace{3mm} Frequency & 10 & & 4000 & MHz & \\
+    \hline
+    Clock output & & & & & \\
+            \hspace{3mm} Peak-to-peak voltage & & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
+            \hspace{3mm} Power & & 5 & & dBm & \\
+    \thickhline
+\end{tabularx}
+\end{threeparttable}
+\end{table}
+
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=6in]{clocker_waveform.png}
+    \caption{Waveform of Clocker at 100 MHz\repeatfootnote{clocker6}}
+\end{figure}
+
+\newpage
+
+\section{Phase-Noise Performance}
+
+Performance measured against 100 MHz Wenzel Quartz, phase-locked to 10MHz Wenzel Blue Top oscillator\footnote{\label{clockerpn}\url{https://github.com/sinara-hw/Clocker/issues/4\#issuecomment-1310591042}}. Blue trace represents measurement against itself for reference.
+
+\begin{figure}[H]
+    \centering
+    \includegraphics[width=6.5in]{clocker_phase_noise.png}
+    \caption{Absolute phase noise of Clocker measured @ 100 MHz (pink trace)\repeatfootnote{clockerpn}}
+\end{figure}
+
+\section{Selecting Clock Source}
+Clock input can be supplied to 7210 Clocker using either the internal MMCX connector or the external SMA connector on the front panel. The selection of clock input is configurable by an SPDT switch, located between the MMCX input connector (\texttt{INT CLK IN}) and the MMCX output connectors. See Figure 5.
+\begin{multicols}{2}
+
+Either \texttt{INT} or \texttt{EXT} can be selected.
+\begin{itemize}
+    \item Internal MMCX (\texttt{INT}) \\
+          Clock signal from the MMCX connector \texttt{INT CLK IN} is distributed to all outputs.
+    \item External SMA (\texttt{EXT}) \\
+          Clock signal from the SMA connector \texttt{CLK IN} on the front panel is distributed to all outputs.
+\end{itemize}
+
+\vspace*{\fill}\columnbreak
+
+\begin{center}
+    \centering
+    \includegraphics[height=1.5in]{clocker_spdt_switch.jpg}
+    \captionof{figure}{Position of the SPDT switch}
+\end{center}
+\end{multicols}
+
+\ordersection{7210 Clocker}
+\finalfootnote{}
+
+\end{document}

Makefile

@@ -0,0 +1,13 @@
+inputs = 1124 2118-2128 2238 2245 4410-4412 4456 5108 5432 5518-5528 5568 7210
+dir = build
+
+all: $(inputs)
+
+$(inputs) : % : %.tex
+	pdflatex -shell-escape $@.tex
+	if ! test -d "$(dir)"; then mkdir build; fi
+	mv $@.pdf build/
+	rm $@.log
+
+clean:
+	rm -r _minted* *.aux *.out

README.md

@@ -0,0 +1,20 @@
+# sinara-hw/datasheets
+
+Repository for Sinara hardware datasheets.
+
+## Build all
+
+```shell
+nix build .#all-pdfs
+```
+
+Output files will be in `result`.
+
+### Build individual sheets
+
+```shell
+nix develop
+make 1124
+```
+
+Output files will be in `build`. Run make twice in a row to get correct output for all LaTeX features, i.e. in particular correct "page x of y" footnotes, which require two passes of the compiler. (`#all-pdfs` already does this automatically). Auxiliary files and clutter can be removed with `make clean`.

datasheet.cls

@@ -40,17 +40,12 @@
 \RequirePackage{threeparttable}
 
 % Align figure and table captions to left.
-\RequirePackage[font=bf, skip=5pt, justification=raggedright, format=hang, singlelinecheck=off]{caption}
+\RequirePackage[font=bf,
-
+    skip=5pt,
-% Format hyperlinks as blue and set PDF title based on \title{} in the document.
+    justification=raggedright,
-\RequirePackage[pdfusetitle]{hyperref}
+    format=hang,
-\hypersetup{
+    singlelinecheck=off,
-    pdftex,
+    hypcap=false]{caption}
-    breaklinks=true,
-    colorlinks=true,
-    linkcolor=.,
-    urlcolor=blue
-}
 
 % Configure page margins
 \RequirePackage{geometry}
@@ -124,6 +119,17 @@
 % No numbering for section titles
 \setcounter{secnumdepth}{0}
 
+% Section and subsection spacing
 \usepackage{titlesec}
 \titlespacing*{\section}{0pt}{.2ex}{.2ex}
 \titlespacing*{\subsection}{0pt}{.2ex}{.2ex}
+
+% Format hyperlinks as blue and set PDF title based on \title{} in the document.
+% Hyperref must be loaded last (in particular after titlesec)
+\RequirePackage[pdfusetitle]{hyperref}
+\hypersetup{
+    breaklinks=true,
+    colorlinks=true,
+    linkcolor=.,
+    urlcolor=blue
+}

examples/cache.py

@@ -0,0 +1,35 @@
+from artiq.experiment import *
+
+
+class CachePut(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("core_cache")
+    
+    @kernel
+    def put(self, key, value):
+        self.core_cache.put(key, value)
+    
+    # First experiment
+    @kernel
+    def run(self):
+        self.put("data", [0xCAFE, 0xDEAD, 0xBEEF])
+
+
+class CacheGet(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("core_cache")
+
+    @kernel
+    def get(self, key):
+        return self.core_cache.get(key)
+    
+    @rpc(flags={"async"})
+    def p(self, p):
+        print([hex(_) for _ in p])
+
+    # Second experiment
+    @kernel
+    def run(self):
+        self.p(self.get("data"))

examples/dds.py

@@ -0,0 +1,134 @@
+from artiq.experiment import *
+from artiq.coredevice.ad9910 import *
+
+
+class Sinusoid(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.cpld = self.get_device("urukul0_cpld")
+        self.dds0 = self.get_device("urukul0_ch0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.cpld.init()
+        self.dds0.init()
+        self.dds0.cfg_sw(True)
+        self.dds0.set_att(6.*dB)
+        self.dds0.set(10*MHz)
+
+
+class SynchronizedSinusoid(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.cpld = self.get_device("urukul0_cpld")
+        self.dds0 = self.get_device("urukul0_ch0")
+        self.dds1 = self.get_device("urukul0_ch1")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.cpld.init()
+
+        self.dds0.init()
+        self.dds0.cfg_sw(True)
+        self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
+        self.dds0.set_att(6.*dB)
+        self.dds1.init()
+        self.dds1.cfg_sw(True)
+        self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
+        self.dds1.set_att(6.*dB)
+
+        self.dds0.set(frequency=10*MHz, phase=0.0)
+        self.dds1.set(frequency=10*MHz, phase=0.25)   # 0.25 turns phase offset
+
+
+class PulseRAM(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.cpld = self.get_device("urukul0_cpld")
+        self.dds0 = self.get_device("urukul0_ch0")
+        self.dds1 = self.get_device("urukul0_ch1")
+
+    def prepare(self):
+        self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
+        self.asf_ram = [0] * len(self.amp)
+
+    @kernel
+    def init_dds(self, dds):
+        self.core.break_realtime()
+        dds.init()
+        dds.set_att(6.*dB)
+        dds.cfg_sw(True)
+
+    @kernel
+    def configure_ram_mode(self, dds):
+        self.core.break_realtime()
+        dds.set_cfr1(ram_enable=0)
+        self.cpld.io_update.pulse_mu(8)
+        self.cpld.set_profile(0)    # Enable the corresponding RAM profile
+                                    # Profile 0 is the default
+        dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
+            step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
+        self.cpld.io_update.pulse_mu(8)
+        dds.amplitude_to_ram(self.amp, self.asf_ram)
+        dds.write_ram(self.asf_ram)
+
+        self.core.break_realtime()
+        dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
+        # Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
+        dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
+
+        self.cpld.io_update.pulse_mu(8)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.cpld.init()
+
+        self.init_dds(self.dds0)
+        self.configure_ram_mode(self.dds0)
+
+
+class AmpRAM(PulseRAM):
+    def prepare(self):
+        # Reversed Order
+        self.amp = [1.0, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, 0.0]
+        self.asf_ram = [0] * len(self.amp)
+
+
+class SynchronizedPulseRAM(PulseRAM):
+    @kernel
+    def configure_ram_mode(self, dds):
+        self.core.break_realtime()
+        dds.set_cfr1(ram_enable=0)
+        self.cpld.io_update.pulse_mu(8)
+        self.cpld.set_profile(0)    # Enable the corresponding RAM profile
+                                    # Profile 0 is the default
+        dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
+            step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
+        self.cpld.io_update.pulse_mu(8)
+        dds.amplitude_to_ram(self.amp, self.asf_ram)
+        dds.write_ram(self.asf_ram)
+
+        self.core.break_realtime()
+        dds.set(frequency=5*MHz, phase=0.0, ram_destination=RAM_DEST_ASF)
+        # Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
+        dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
+
+        self.cpld.io_update.pulse_mu(8)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.cpld.init()
+
+        self.init_dds(self.dds0)
+        self.init_dds(self.dds1)
+        self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
+        self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
+
+        self.configure_ram_mode(self.dds0)
+        self.configure_ram_mode(self.dds1)

examples/dma.py

@@ -0,0 +1,29 @@
+from artiq.experiment import *
+
+
+class DMA(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("core_dma")
+        self.setattr_device("led0")
+
+    @kernel
+    def record(self):
+        with self.core_dma.record("led_blink"):
+            delay(100*ms)
+            self.led0.on()
+            delay(100*ms)
+            self.led0.off()
+
+    @kernel
+    def playback(self, n):
+        handle = self.core_dma.get_handle("led_blink")
+        self.core.break_realtime()
+        for _ in range(n):
+            self.core_dma.playback_handle(handle)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.record()
+        self.playback(2)

examples/pll.py

@@ -0,0 +1,44 @@
+from artiq.experiment import *
+
+
+class MirnyEnv(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.cpld = self.get_device("mirny0_cpld")
+        self.pll0 = self.get_device("mirny0_ch0")
+
+    @kernel
+    def init_mirny(self):
+        self.core.reset()
+        self.cpld.init()
+        self.pll0.init()
+        self.pll0.set_frequency(1*GHz)
+        self.pll0.set_att(12*dB)
+        self.pll0.sw.on()
+
+
+class PowerControl(MirnyEnv):
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.init_mirny()
+
+        # Run other code here
+        delay(5*s)
+        self.pll0.set_output_power_mu(0)
+        print(self.pll0.output_power_mu())
+
+
+class ToggleSwitch(MirnyEnv):
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.init_mirny()
+
+        delay_mu(8)     # Avoid RTIO collision
+        self.pll0.sw.off()
+        delay(1*s)
+        
+        while True:
+            self.pll0.sw.pulse(100*us)
+            delay(900*us)

examples/sampler.py

@@ -0,0 +1,21 @@
+from artiq.experiment import *
+
+
+class SamplerInit(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.sampler = self.get_device("sampler0")
+
+    def prepare(self):
+        self.smp = [0.0]*8
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.sampler.init()
+        delay(5*ms)
+        for i in range(8):
+            self.sampler.set_gain_mu(i, 0)
+            delay(100*us)
+        self.sampler.sample(self.smp)

examples/spi.py

@@ -0,0 +1,49 @@
+from artiq.experiment import *
+from artiq.coredevice import spi2 as spi
+
+
+SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
+              0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY |
+              0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
+              0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
+
+CLK_DIV = 125
+
+
+class SPIWrite(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.spi = self.get_device("dio_spi0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110)
+        self.spi.write(0x13 << 24)      # Shift the bits to the MSBs.
+                                        # Since SPI_LSB_FIRST is NOT set,
+                                        # SPI Machine will shift out bits from
+                                        # the MSB of the `data` register.`
+        self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110)
+        self.spi.write(0xDEADBEEF)
+
+
+class SPIRead(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.spi = self.get_device("dio_spi0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001)
+        self.spi.write(0x81 << 24)      # Shift the bits to the MSBs.
+                                        # Since SPI_LSB_FIRST is NOT set,
+                                        # SPI Machine will shift out bits from
+                                        # the MSB of the `data` register.`
+        self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
+                                32, CLK_DIV, 0b001)
+        self.spi.write(0)               # write() performs the SPI transfer.
+                                        # As suggested by the timing diagram,
+                                        # the exact value of this argument
+                                        # does not matter.
+        print(self.spi.read())

examples/suservo.py

@@ -0,0 +1,33 @@
+from artiq.experiment import *
+
+
+class SUServoExample(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.suservo = self.get_device("suservo0")
+        self.suschannel0 = self.get_device("suservo0_ch0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.suservo.init()
+        self.suservo.set_pgia_mu(0, 0)  # unity gain
+        self.suservo.cplds[0].set_att(0, 15.)
+        self.suschannel0.set_y(profile=0, y=0.) # Clear integrator
+        self.suschannel0.set_iir(
+            profile=0,
+            adc=0,          # take data from Sampler channel 0
+            kp=-1.,         # -1 P gain
+            ki=0./s,        # no integrator gain
+            g=0.,           # no integrator gain limit
+            delay=0.        # no IIR update delay after enabling
+        )
+        self.suschannel0.set_dds(
+            profile=0,
+            offset=-.3,     # 3 V with above PGIA settings
+            frequency=10*MHz,
+            phase=0.)
+        # enable RF, IIR updates and set profile
+        self.suschannel0.set(en_out=1, en_iir=1, profile=0)
+        self.suservo.set_config(enable=1)

examples/ttl.py

@@ -0,0 +1,75 @@
+from artiq.experiment import *
+
+
+class OnePulsePerSecond(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttl0 = self.get_device("ttl0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        while True:
+            self.ttl0.pulse(500*ms)
+            delay(500*ms)
+
+
+class MorseCode(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.led = self.get_device("led0")
+
+    def prepare(self):
+        # As of ARTIQ-6, the ARTIQ compiler has limited string handling
+        # capabilities, so we pass a list of integers instead.
+        message = ".- .-. - .. --.-"
+        self.commands = [{".": 1, "-": 2, " ": 3}[c] for c in message]
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        for cmd in self.commands:
+            if cmd == 1:
+                self.led.pulse(100*ms)
+                delay(100*ms)
+            if cmd == 2:
+                self.led.pulse(300*ms)
+                delay(100*ms)
+            if cmd == 3:
+                delay(700*ms)
+
+
+class SoftwareEdgeCount(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttl0 = self.get_device("ttl0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        gate_end_mu = self.ttl0.gate_rising(1*ms)
+        counts = self.ttl0.count(gate_end_mu)
+        print(counts)
+
+
+class ShortPulse(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttl0 = self.get_device("ttl0")
+    
+    @kernel
+    def run(self):
+        self.core.reset()
+        delay(6*ns)             # Coarse RTIO period: 0 - 7  ns
+        self.ttl0.pulse(3*ns)   # Coarse RTIO period: 8 - 15 ns
+
+
+class ClockGen(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttl0 = self.get_device("ttl0")
+    
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.ttl0.set(62.5*MHz)

examples/ttl_in.py

@@ -0,0 +1,98 @@
+from artiq.experiment import *
+
+
+class SoftwareEdgeCount(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttlin = self.get_device("ttl0")
+        self.ttlout = self.get_device("ttl7")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        gate_start_mu = now_mu()
+        # Start input gate & advance timeline cursor to gate_end_mu
+        gate_end_mu = self.ttlin.gate_rising(1*ms)
+        at_mu(gate_start_mu)
+
+        for _ in range(64):
+            self.ttlout.pulse(8*ns)
+            delay(8*ns)
+
+        counts = self.ttlin.count(gate_end_mu)
+        print(counts)
+
+
+class EdgeCounter(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.edgecounter0 = self.get_device("ttl0_counter")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.edgecounter0.gate_rising(1*ms)
+        counts = self.edgecounter0.fetch_count()
+        print(counts)
+
+
+class ExternalTrigger(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttlin = self.get_device("ttl0")
+        self.ttlout = self.get_device("ttl4")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        gate_end_mu = self.ttlin.gate_rising(5*ms)
+        timestamp_mu = self.ttlin.timestamp_mu(gate_end_mu)
+        at_mu(timestamp_mu + self.core.seconds_to_mu(10*ms))
+        self.ttlout.pulse(1*us)
+
+
+import time
+
+
+class MeanTimestampDuration(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttlin = self.get_device("ttl0")
+        self.ttlclk = self.get_device("ttl7")
+    
+    @kernel
+    def get_timestamp_duration(self, pulse_num) -> TInt64:
+        self.core.break_realtime()
+        delay(1*ms)
+        gate_start_mu = now_mu()
+        # Start input gate & advance timeline cursor to gate_end_mu
+        gate_end_mu = self.ttlin.gate_rising(1*ms)
+        at_mu(gate_start_mu)
+
+        self.ttlclk.set_mu(0x800000)
+        delay(16*pulse_num*ns)
+        self.ttlclk.set_mu(0)
+
+        # Guarantee t0 > gate_end_mu
+        # Otherwise timestamp_mu may wait for pulses till gate_end_mu
+        rtio_time_mu = self.core.get_rtio_counter_mu()
+        sleep_mu = float(gate_end_mu - rtio_time_mu)
+        self.rpc_sleep(self.core.mu_to_seconds(sleep_mu))
+
+        t0 = self.core.get_rtio_counter_mu()
+        while self.ttlin.timestamp_mu(gate_end_mu) >= 0:
+            pass
+        t1 = self.core.get_rtio_counter_mu()
+        return t1 - t0
+
+    @rpc
+    def rpc_sleep(self, duration):
+        time.sleep(duration)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        t64 = self.get_timestamp_duration(64)
+        t8 = self.get_timestamp_duration(8)
+        print("Mean timestamp_mu duration:")
+        print(self.core.mu_to_seconds((t64 - t8)/((64 + 1) - (8 + 1))))

examples/zotino.py

@@ -0,0 +1,49 @@
+from artiq.experiment import *
+from scipy import signal
+import numpy
+
+
+class Voltage(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.zotino = self.get_device("zotino0")
+
+    def prepare(self):
+        self.channels = [0, 1, 2, 3]
+        self.voltages = [1.0, 2.0, 3.0, 4.0]
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.zotino.init()
+
+        delay(1*ms)
+        self.zotino.set_dac(self.voltages, self.channels)
+
+
+class TriangularWave(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.zotino = self.get_device("zotino0")
+
+    def prepare(self):
+        self.period = 0.1*s
+        self.sample = 128
+        t = numpy.linspace(0, 1, self.sample)
+        self.voltages = 8*signal.sawtooth(2*numpy.pi*t, 0.5)
+        self.interval = self.period/self.sample
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.zotino.init()
+
+        delay(1*ms)
+
+        counter = 0
+        while True:
+            self.zotino.set_dac([self.voltages[counter]], [0])
+            counter = (counter + 1) % self.sample
+            delay(self.interval)

flake.lock

@@ -0,0 +1,27 @@
+{
+  "nodes": {
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1729880355,
+        "narHash": "sha256-RP+OQ6koQQLX5nw0NmcDrzvGL8HDLnyXt/jHhL1jwjM=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "18536bf04cd71abd345f9579158841376fdd0c5a",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixos-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "nixpkgs": "nixpkgs"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}

flake.nix

@@ -0,0 +1,43 @@
+{
+  description = "Sinara datasheets";
+
+  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
+
+  outputs = { self, nixpkgs }:
+    let
+      pkgs = import nixpkgs { system = "x86_64-linux";};
+
+      latex-pkgs = pkgs.texlive.combine {
+          inherit (pkgs.texlive)
+            scheme-small collection-latexextra collection-fontsextra
+            collection-fontsrecommended cbfonts-fd cbfonts palatino textgreek helvetic
+            greek-inputenc maths-symbols mathpazo babel isodate tcolorbox etoolbox
+            pgfplots visualtikz quantikz tikz-feynman circuitikz
+            minted pst-graphicx;
+        };
+
+      python-pkgs = with pkgs.python3Packages; [ pygments ];
+
+    in rec {
+
+      all-pdfs = pkgs.stdenvNoCC.mkDerivation rec {
+        name = "datasheets-pdfs";
+        src = self;
+        buildInputs = [ latex-pkgs ] ++ python-pkgs;
+        # is there a better way to get .aux/.out files correct than to just run latexpdf twice?
+        buildPhase = ''
+          make all
+          make all
+        '';
+        installPhase = ''
+          mkdir $out
+          cp build/*.pdf $out
+        '';
+      };
+
+      devShells.x86_64-linux.default = pkgs.mkShell {
+          name = "datasheet-dev-shell";
+          buildInputs = [ latex-pkgs ] ++ python-pkgs;
+      };
+  };
+}

footnote.tex

@@ -0,0 +1,3 @@
+\begin{footnotesize}
+Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
+\end{footnotesize}

preamble.tex

@@ -0,0 +1,64 @@
+\documentclass[10pt]{datasheet}
+\usepackage{palatino}
+\usepackage{textgreek}
+\usepackage{minted}
+\usepackage{tcolorbox}
+\usepackage{etoolbox}
+
+\usepackage[justification=centering]{caption}
+
+\usepackage[utf8]{inputenc}
+\usepackage[english]{babel}
+\usepackage[english]{isodate}
+
+\usepackage{graphicx}
+\usepackage{subfig}
+
+\usepackage{tikz}
+\usepackage{pgfplots}
+\pgfplotsset{compat=1.18}
+\usepackage{circuitikz}
+\usepackage{pifont}
+
+\usetikzlibrary{calc}
+\usetikzlibrary{fit,backgrounds}
+
+\newcommand*{\twocm}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
+\newcommand*{\fourcm}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
+\newcommand{\inputcolorboxminted}[3][4]{%
+    \begin{tcolorbox}[colback=white]
+    \inputminted[#2, gobble=#1]{python}{#3}
+    \end{tcolorbox}
+}
+\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
+
+\newcommand*{\sourcesection}[2]{
+\section{Source}
+#1, like all the Sinara hardware family, is open-source hardware, and design files (schematics, PCB layouts, BOMs) can be found in detail at the repository \url{#2}.
+}
+
+\newcommand*{\sourcesectiond}[4]{
+\section{Source}
+#1 and #2, like all the Sinara hardware family, are open-source hardware, and design files (schematics, PCB layouts,
+BOMs) can be found in detail at the repositories \url{#3} and \url{#4}.
+}
+
+\newcommand*{\ordersection}[1]{
+\section{Ordering Information}
+To order, please visit \url{https://m-labs.hk} and choose #1 in the ARTIQ/Sinara hardware selection tool. Cards can be ordered as part of a fully-featured ARTIQ/Sinara crate or standalone through the 'Spare cards' option. Otherwise, orders can also be made by writing directly to \url{mailto:sales@m-labs.hk}.
+}
+
+\newcommand{\codesection}[1] {
+\section{Example ARTIQ Code}
+The sections below demonstrate simple usage scenarios of extensions on the ARTIQ control system. These extensions make use of the resources of the #1. They do not exhaustively demonstrate all the features of the ARTIQ system. 
+
+The full documentation for ARTIQ software and gateware, including the guide for its use, is available at \url{https://m-labs.hk/artiq/manual/}. Please consult the manual for details and reference material of the functions and structures used here.
+}
+
+\newcommand*{\finalfootnote}{
+\section*{}
+\vspace*{\fill}
+\begin{footnotesize}
+    Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
+\end{footnotesize}
+}

shell.nix

@@ -1,44 +0,0 @@
-let
-  pkgs = import <nixpkgs> {};
-in
-  pkgs.mkShell {
-    buildInputs = [
-
-      #pkgs.texlive.combined.scheme-small 
-
-      (pkgs.texlive.combine {
-        inherit (pkgs.texlive) 
-        scheme-small
-        collection-latexextra
-        collection-fontsextra
-        collection-fontsrecommended
-        palatino
-        textgreek
-        minted
-        tcolorbox
-        etoolbox
-        maths-symbols
-        greek-inputenc
-        babel
-        isodate
-        pst-graphicx
-        visualtikz
-        quantikz
-        tikz-feynman
-        pgfplots
-        cbfonts-fd
-        cbfonts
-        mathpazo
-        helvetic
-        circuitikz  ;
-
-        # To compile, call:
-        # $ pdflatex -shell-escape xxx.tex
-        # if missing packages, you can search if the required tex packages is in nixpkgs or not from here
-        # https://raw.githubusercontent.com/NixOS/nixpkgs/master/pkgs/tools/typesetting/tex/texlive/pkgs.nix
-        # if available, just add it to the above list 
-
-      })
-    ];
-  }
-

template.tex

@@ -0,0 +1,63 @@
+\include{preamble.tex}
+\graphicspath{{images}}
+
+\title{BOARD NAME}
+\author{M-Labs Limited}
+\date{October 2024}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+\item{features}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+\item{applications}
+\end{itemize}
+
+\section{General Description}
+
+% Switch to next column
+\vfill\break
+
+\begin{figure}[h]
+    \centering
+    \scalebox{1.15}{
+    \begin{circuitikz}[european, every label/.append style={align=center}]
+        \begin{scope}[]
+            % if applicable
+        \end{scope}
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    % card photo
+    % front panel
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\section{Specifications}
+
+\newpage
+
+\section{Example ARTIQ code}
+\section*{}
+\vspace*{\fill}
+
+\input{footnote.tex}
+
+\end{document}