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Sinara datasheets
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occheung 2d0a866274 2238: add spec on max voltage with term 
Updates #35.
Same termination structure as bnc/sma-ttl card.
Technically the max allowable voltage with termination is a bit higher than 5V.
But it seems that it will still exceed the termination resistor rating limit at 5.5V.
The only method of acquiring V_ds & other parameters is by eye-balling the I-V curve of the MOSFET, which is not precise.
So the calculation assumes V_ds=0, just to be conservative.
2022-06-17 16:07:21 +08:00
examples examples: move SPI examples to spi.py 2022-06-16 16:00:22 +08:00
2118-2128.tex 2118-2128: separate term rating to another spec 2022-06-17 16:06:26 +08:00
2238.tex 2238: add spec on max voltage with term 2022-06-17 16:07:21 +08:00
2245.tex examples: move SPI examples to spi.py 2022-06-16 16:00:22 +08:00
4410-4412.tex 4410-4412: remove mention of external sync signal distribution 2022-06-08 17:21:27 +08:00
4456.tex 4456: clarify setup for the tests 2022-02-14 11:02:07 +08:00
5108.tex 5108: mention possible SMA breakout option 2022-06-09 11:51:44 +08:00
5432.tex 5432: fix card name 2022-02-04 13:49:10 +08:00
5518-5528.tex 5518-5528: init 2022-06-08 17:22:55 +08:00
5568.tex 5568: init 2022-06-16 16:02:47 +08:00
artiq_sinara.pdf initial commit 2021-07-19 16:49:16 +08:00
att_glitch_bitflip.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
att_glitch_carry.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
bnc_idc_assembly.pdf 5518-5528: init 2022-06-08 17:22:55 +08:00
bnc_idc_drawings.pdf 5518-5528: init 2022-06-08 17:22:55 +08:00
BNC_IDC_FP.jpg 5518-5528: init 2022-06-08 17:22:55 +08:00
bnc_ttl_assembly.pdf 2118-2128: add BNC-TTL front panels 2022-06-09 16:54:00 +08:00
bnc_ttl_drawings.pdf 2118-2128: add BNC-TTL front panels 2022-06-09 16:54:00 +08:00
bnc_ttl_min_pulse_width.png add missing plot in b476c178 2022-06-17 13:34:56 +08:00
bnc_ttl_switches.jpg ttl: reduce image size for switches 2022-01-11 17:18:30 +08:00
datasheet.cls initial commit 2021-07-19 16:49:16 +08:00
dds_assembly.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
dds_drawings.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
DIO_BNC_FP.jpg fp pictures: png -> jpg 2022-01-26 09:57:30 +08:00
DIO_MCX_FP.pdf add front panel pictures to MCX/LVDS-TTL 2022-01-25 15:54:28 +08:00
DIO_RJ45_FP.pdf add front panel pictures to MCX/LVDS-TTL 2022-01-25 15:54:28 +08:00
DIO_SMA_FP.jpg fp pictures: png -> jpg 2022-01-26 09:57:30 +08:00
hd68_idc_connection.pdf 5568: init 2022-06-16 16:02:47 +08:00
HD68_IDC_FP.pdf 5568: init 2022-06-16 16:02:47 +08:00
idc_cm_choke.pdf 5518-5528: init 2022-06-08 17:22:55 +08:00
lvds_ttl_switches.jpg ttl: reduce image size for switches 2022-01-11 17:18:30 +08:00
mcx_ttl_switches.jpg ttl: reduce image size for switches 2022-01-11 17:18:30 +08:00
Mirny_FP.pdf 4456: init 2022-02-04 17:18:15 +08:00
mirny_phase_noise_cm_choke.png 4456: init 2022-02-04 17:18:15 +08:00
mirny_phase_noise_frequency.png 4456: init 2022-02-04 17:18:15 +08:00
nyquist_rejection_400mhz.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
nyquist_rejection_450mhz.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
photo2118.jpg 2118: add photo 2021-12-23 12:56:49 +08:00
photo2128.jpg initial commit 2021-07-19 16:49:16 +08:00
photo2238.jpg add front panel pictures to MCX/LVDS-TTL 2022-01-25 15:54:28 +08:00
photo2245.jpg 2245: init 2021-12-31 17:34:16 +08:00
photo4410.jpg init urukul 4410 2021-11-30 14:17:02 +08:00
photo4456.jpg 4456: init 2022-02-04 17:18:15 +08:00
photo5108.jpg 5108: init Sampler 2022-01-25 09:39:20 +08:00
photo5432.jpg 5432: init 2021-12-09 12:33:42 +08:00
photo5518.jpg 5518-5528: init 2022-06-08 17:22:55 +08:00
photo5568.jpg 5568: init 2022-06-16 16:02:47 +08:00
rf_transient.jpg 4410-4412: add figures 2021-12-24 16:49:45 +08:00
sampler_assembly.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
sampler_drawings.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
Sampler_FP.jpg fp pictures: png -> jpg 2022-01-26 09:57:30 +08:00
sampler_large_signal_bw.png 5108: init Sampler 2022-01-25 09:39:20 +08:00
sampler_noise_no_term.png 5108: init Sampler 2022-01-25 09:39:20 +08:00
sampler_noise_term.png 5108: init Sampler 2022-01-25 09:39:20 +08:00
sampler_small_signal_bw.png 5108: init Sampler 2022-01-25 09:39:20 +08:00
sampler_switches.jpg 5108: init Sampler 2022-01-25 09:39:20 +08:00
sampler_xt_35khz.png 5108: init Sampler 2022-01-25 09:39:20 +08:00
sampler_xt_300khz_1x_gain.png 5108: init Sampler 2022-01-25 09:39:20 +08:00
sampler_xt_300khz.png 5108: init Sampler 2022-01-25 09:39:20 +08:00
shell.nix update 2128 2021-07-27 17:10:27 +08:00
sma_idc_assembly.pdf 5518-5528: init 2022-06-08 17:22:55 +08:00
sma_idc_drawings.pdf 5518-5528: init 2022-06-08 17:22:55 +08:00
SMA_IDC_FP.pdf 5518-5528: init 2022-06-08 17:22:55 +08:00
sma_ttl_assembly.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
sma_ttl_drawings.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
sma_ttl_switches.jpg ttl: reduce image size for switches 2022-01-11 17:18:30 +08:00
urukul_6dbm_harmonics.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
urukul_10dbm_harmonics.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
urukul_clock_phase_noise.jpg 4410-4412: add graphs for phase noise/harmonic contents 2021-12-22 12:17:23 +08:00
urukul_dip_switch.jpg 4410-4412: add DIP switch doc 2022-01-10 15:20:21 +08:00
Urukul_FP.jpg fp pictures: png -> jpg 2022-01-26 09:57:30 +08:00
urukul_harmonics.png 4410-4412: add graphs for phase noise/harmonic contents 2021-12-22 12:17:23 +08:00
urukul_xo_phase_noise.jpg 4410-4412: add graphs for phase noise/harmonic contents 2021-12-22 12:17:23 +08:00
zotino_assembly.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
zotino_drawings.pdf fp: re-edit & change format to pdf 2022-01-25 14:57:54 +08:00
zotino_fext.png 5432: add plots 2021-12-30 15:00:43 +08:00
Zotino_FP.jpg fp pictures: png -> jpg 2022-01-26 09:57:30 +08:00
zotino_step_response_falling.png 5432: add plots 2021-12-30 15:00:43 +08:00
zotino_step_response_rising.png 5432: add plots 2021-12-30 15:00:43 +08:00