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Sinara datasheets
68 Commits 2 Branches 0 Tags 12 MiB
TeX 99.4%
Nix 0.5%
Makefile 0.1%
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occheung ae4015fbd7 2238: simplify diagram 
Merging a transiceiver on the baseboard and another transceiver on the mezzanine into 2x transceivers.
So the EEM line does not split into odd/even transceivers, and no more jumping lines/hyper-abstract connections.

The termination switches still repsect the physical configuration, so it is not the cleanest.
Though. the connections should be easily understood.
2022-01-07 13:57:22 +08:00
2118-2128.tex slightly enlarge FP drawings 2022-01-07 10:37:16 +08:00
2238.tex 2238: simplify diagram 2022-01-07 13:57:22 +08:00
2245.tex 2245: remove channel-to-channel skew 2022-01-04 13:48:40 +08:00
4410-4412.tex slightly enlarge FP drawings 2022-01-07 10:37:16 +08:00
5432.tex slightly enlarge FP drawings 2022-01-07 10:37:16 +08:00
artiq_sinara.pdf initial commit 2021-07-19 16:49:16 +08:00
att_glitch_bitflip.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
att_glitch_carry.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
datasheet.cls initial commit 2021-07-19 16:49:16 +08:00
DIO_BNC_FP.png 2118-2128: add front panel figures 2022-01-06 11:46:30 +08:00
DIO_SMA_assembly.jpg 2118-2128: add front panel figures 2022-01-06 11:46:30 +08:00
DIO_SMA_drawings.jpg 2118-2128: add front panel figures 2022-01-06 11:46:30 +08:00
DIO_SMA_FP.png 2118-2128: add front panel figures 2022-01-06 11:46:30 +08:00
nyquist_rejection_400mhz.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
nyquist_rejection_450mhz.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
photo2118.jpg 2118: add photo 2021-12-23 12:56:49 +08:00
photo2128.jpg initial commit 2021-07-19 16:49:16 +08:00
photo2238.jpg 2238: add photo 2022-01-03 17:21:34 +08:00
photo2245.jpg 2245: init 2021-12-31 17:34:16 +08:00
photo4410.jpg init urukul 4410 2021-11-30 14:17:02 +08:00
photo5432.jpg 5432: init 2021-12-09 12:33:42 +08:00
rf_transient.jpg 4410-4412: add figures 2021-12-24 16:49:45 +08:00
shell.nix update 2128 2021-07-27 17:10:27 +08:00
urukul_6dbm_harmonics.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
urukul_10dbm_harmonics.png 4410-4412: add figures 2021-12-24 16:49:45 +08:00
Urukul_assembly.jpg 4410: add front panel drawings 2022-01-06 17:29:38 +08:00
urukul_clock_phase_noise.jpg 4410-4412: add graphs for phase noise/harmonic contents 2021-12-22 12:17:23 +08:00
Urukul_drawings.jpg 4410: add front panel drawings 2022-01-06 17:29:38 +08:00
Urukul_FP.png 4410: add front panel drawings 2022-01-06 17:29:38 +08:00
urukul_harmonics.png 4410-4412: add graphs for phase noise/harmonic contents 2021-12-22 12:17:23 +08:00
urukul_xo_phase_noise.jpg 4410-4412: add graphs for phase noise/harmonic contents 2021-12-22 12:17:23 +08:00
Zotino_assembly.jpg 5432: add front panel 2022-01-07 10:33:14 +08:00
Zotino_drawings.jpg 5432: add front panel 2022-01-07 10:33:14 +08:00
zotino_fext.png 5432: add plots 2021-12-30 15:00:43 +08:00
Zotino_FP.png 5432: add front panel 2022-01-07 10:33:14 +08:00
zotino_step_response_falling.png 5432: add plots 2021-12-30 15:00:43 +08:00
zotino_step_response_rising.png 5432: add plots 2021-12-30 15:00:43 +08:00