4410-4412: get example code from file
Updates #24. Added example files for DDS and SUServo respectively.
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4410-4412.tex
144
4410-4412.tex
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@ -4,8 +4,6 @@
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\usepackage{minted}
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\usepackage{tcolorbox}
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\usepackage{etoolbox}
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\BeforeBeginEnvironment{minted}{\begin{tcolorbox}[colback=white]}%
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\AfterEndEnvironment{minted}{\end{tcolorbox}}%
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\usepackage[justification=centering]{caption}
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@ -69,6 +67,11 @@ RF switches (1ns temporal resolution) on each channel provides 70 dB isolation.
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\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
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\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
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\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
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\newcommand{\inputcolorboxminted}[2]{%
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\begin{tcolorbox}[colback=white]
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\inputminted[#1, gobble=4]{python}{#2}
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\end{tcolorbox}
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}
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\begin{figure}[h]
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\centering
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@ -688,37 +691,13 @@ Generate a 10MHz sinusoid from RF0 with full scale amplitude, attenuated by 6 dB
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Both the CPLD and the DDS channels should be initialized.
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By default, AD9910 single-tone profiles are programmed to profile 7.
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\begin{minted}{python}
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@kernel
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def run(self):
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self.core.reset()
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self.cpld.init()
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self.dds0.init()
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self.dds0.cfg_sw(True)
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self.dds0.set_att(6.*dB)
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self.dds0.set(10*MHz)
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\end{minted}
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\inputcolorboxminted{firstline=11,lastline=18}{examples/dds.py}
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If the synchronization feature of AD9910 was enabled, RF signal across different channels of the same Urukul can be synchronized.
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For example, phase-coherent RF signal can be produced on both channel 0 and channel 1 after configuring an appropriate phase mode.
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\begin{minted}{python}
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@kernel
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def run(self):
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self.core.reset()
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self.cpld.init()
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self.dds0.init()
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self.dds0.cfg_sw(True)
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self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds0.set_att(6.*dB)
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self.dds1.init()
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self.dds1.cfg_sw(True)
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self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds1.set_att(6.*dB)
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\inputcolorboxminted{firstline=28,lastline=43}{examples/dds.py}
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self.dds0.set(frequency=10*MHz, phase=0.0)
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self.dds1.set(frequency=10*MHz, phase=0.25) # 0.25 turns phase offset
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\end{minted}
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Note that the phase difference between the 2 channels might not be exactly 0.25 turns, but it is a constant.
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It can be negated by adjusting the \texttt{phase} parameter.
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@ -727,49 +706,7 @@ It can be negated by adjusting the \texttt{phase} parameter.
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This examples demonstrates that the RF signal can be modulated by amplitude using the RAM modulation feature of AD9910.
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By default, RAM profiles are programmed to profile 0.
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\begin{minted}{python}
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from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP
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def prepare(self):
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self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
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self.asf_ram = [0] * len(self.amp)
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@kernel
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def init_dds(self, dds):
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self.core.break_realtime()
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dds.init()
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dds.set_att(6.*dB)
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dds.cfg_sw(True)
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@kernel
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def configure_ram_mode(self, dds):
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self.core.break_realtime()
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dds.set_cfr1(ram_enable=0)
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self.cpld.io_update.pulse_mu(8)
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self.cpld.set_profile(0) # Enable the corresponding RAM profile
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# Profile 0 is the default
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dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
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step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
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self.cpld.io_update.pulse_mu(8)
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dds.amplitude_to_ram(self.amp, self.asf_ram)
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dds.write_ram(self.asf_ram)
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self.core.break_realtime()
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dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
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# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
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dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
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self.cpld.io_update.pulse_mu(8)
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.cpld.init()
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self.init_dds(self.dds0)
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self.configure_ram_mode(self.dds0)
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\end{minted}
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\inputcolorboxminted{firstline=53,lastline=91}{examples/dds.py}
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The generated RF output of the above example consists of the following features in sequence:
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\begin{enumerate}
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@ -815,12 +752,8 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
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\subsection{Simple Amplitude Ramp (AD9910 Only)}
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An amplitude ramp of an RF signal can be generated by modifying the \texttt{self.amp} array in the previous example.
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\begin{minted}{python}
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def prepare(self):
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# Reversed Order
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self.amp = [1.0, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, 0.0]
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self.asf_ram = [0] * len(self.amp)
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\end{minted}
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\inputcolorboxminted{firstline=95,lastline=98}{examples/dds.py}
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The generated RF output has an incrementing amplitude scale factor (ASF), increasing by 0.1 at every microsecond.
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Once the ASF reaches 1.0, it drops back to 0.0 at the next microsecond.
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@ -871,25 +804,13 @@ Urukul was operated with a 50$\Omega$ termination to produce the waveform.
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Multiple RAM channels can also be synchronized.
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Similar to the 10 MHz single-tone RF signals, specify \texttt{phase} when calling \texttt{dds.set()} in \texttt{configure\char`_ram\char`_mode}.
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For example, set phase to 0 for the channels (\texttt{phase=0.0}).
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\begin{minted}{python}
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dds.set(frequency=5*MHz, phase=0.0, ram_destination=RAM_DEST_ASF)
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\end{minted}
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\inputcolorboxminted{firstline=116,lastline=116}{examples/dds.py}
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Then, replace the \texttt{run()} function with the following.
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\begin{minted}{python}
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.cpld.init()
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self.init_dds(self.dds0)
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self.init_dds(self.dds1)
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self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
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\inputcolorboxminted{firstline=122,lastline=134}{examples/dds.py}
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self.configure_ram_mode(self.dds0)
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self.configure_ram_mode(self.dds1)
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\end{minted}
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Two phase-coherent RF signal with the same waveform as the previous figure (from either RAM examples) should be generated.
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\subsection{Voltage-controlled DDS Amplitude (SU-Servo Only)}
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@ -899,41 +820,17 @@ Amplitude of the DDS output can be controlled by the ADC input of the Sampler th
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In the following example, the amplitude of DDS is proportional to the ADC input from Sampler.
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First, initialize the RTIO, SU-Servo and its channel.
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Note that the programmable gain of the Sampler is $10^0=1$, the input range is [-10V, 10V].
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\begin{minted}{python}
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.suservo.init()
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self.suservo.set_pgia_mu(0, 0) # unity gain
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self.suservo.cplds[0].set_att(0, 15.)
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self.channel.set_y(profile=0, y=0.) # Clear integrator
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\end{minted}
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\inputcolorboxminted{firstline=14,lastline=21}{examples/suservo.py}
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Next, setup the PI control as an IIR filter. It has -1 proportional gain $k_p$ and no integrator gain $k_i$.
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\begin{minted}{python}
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self.channel.set_iir(
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profile=0,
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adc=0, # take data from Sampler channel 0
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kp=-1., # -1 P gain
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ki=0./s, # no integrator gain
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g=0., # no integrator gain limit
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delay=0. # no IIR update delay after enabling
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)
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\end{minted}
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\inputcolorboxminted{firstline=22,lastline=29}{examples/suservo.py}
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Then, configure the DDS frequency to 10 MHz with 3V input offset.
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When input voltage $\geq$ offset voltage, the DDS output amplitude is 0.
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\begin{minted}{python}
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self.channel.set_dds(
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profile=0,
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offset=-.3, # 3V with above PGIA settings
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# Note the inverted sign
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frequency=10*MHz,
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phase=0.)
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\end{minted}
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\inputcolorboxminted{firstline=30,lastline=34}{examples/suservo.py}
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SU-Servo encodes the ADC voltage in a linear scale [-1, 1].
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Therefore, 3V is converted to 0.3.
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@ -941,10 +838,7 @@ Note that the ASF of all DDS channels are capped at 1.0, the amplitude clips whe
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Finally, enable the SU-Servo channel with the IIR filter programmed beforehand.
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\begin{minted}{python}
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self.channel.set(en_out=1, en_iir=1, profile=0)
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self.suservo.set_config(enable=1)
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\end{minted}
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\inputcolorboxminted{firstline=36,lastline=37}{examples/suservo.py}
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A 10 MHz DDS signal is generated from the example above, with amplitude controllable by ADC.
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The RMS voltage of the DDS channel against the ADC voltage is plotted.
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@ -0,0 +1,134 @@
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from artiq.experiment import *
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from artiq.coredevice.ad9910 import *
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class Sinusoid(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.cpld = self.get_device("urukul0_cpld")
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self.dds0 = self.get_device("urukul0_ch0")
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@kernel
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def run(self):
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self.core.reset()
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self.cpld.init()
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self.dds0.init()
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self.dds0.cfg_sw(True)
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self.dds0.set_att(6.*dB)
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self.dds0.set(10*MHz)
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class SynchronizedSinusoid(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.cpld = self.get_device("urukul0_cpld")
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self.dds0 = self.get_device("urukul0_ch0")
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self.dds1 = self.get_device("urukul0_ch1")
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@kernel
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def run(self):
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self.core.reset()
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self.cpld.init()
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self.dds0.init()
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self.dds0.cfg_sw(True)
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self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds0.set_att(6.*dB)
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self.dds1.init()
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self.dds1.cfg_sw(True)
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self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds1.set_att(6.*dB)
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self.dds0.set(frequency=10*MHz, phase=0.0)
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self.dds1.set(frequency=10*MHz, phase=0.25) # 0.25 turns phase offset
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class PulseRAM(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.cpld = self.get_device("urukul0_cpld")
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self.dds0 = self.get_device("urukul0_ch0")
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self.dds1 = self.get_device("urukul0_ch1")
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def prepare(self):
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self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
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self.asf_ram = [0] * len(self.amp)
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@kernel
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def init_dds(self, dds):
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self.core.break_realtime()
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dds.init()
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dds.set_att(6.*dB)
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dds.cfg_sw(True)
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@kernel
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def configure_ram_mode(self, dds):
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self.core.break_realtime()
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dds.set_cfr1(ram_enable=0)
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self.cpld.io_update.pulse_mu(8)
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self.cpld.set_profile(0) # Enable the corresponding RAM profile
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# Profile 0 is the default
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dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
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step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
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self.cpld.io_update.pulse_mu(8)
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dds.amplitude_to_ram(self.amp, self.asf_ram)
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dds.write_ram(self.asf_ram)
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self.core.break_realtime()
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dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
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# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
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dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
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self.cpld.io_update.pulse_mu(8)
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.cpld.init()
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self.init_dds(self.dds0)
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self.configure_ram_mode(self.dds0)
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class AmpRAM(PulseRAM):
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def prepare(self):
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# Reversed Order
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self.amp = [1.0, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.1, 0.0]
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self.asf_ram = [0] * len(self.amp)
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class SynchronizedPulseRAM(PulseRAM):
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@kernel
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def configure_ram_mode(self, dds):
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self.core.break_realtime()
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dds.set_cfr1(ram_enable=0)
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self.cpld.io_update.pulse_mu(8)
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self.cpld.set_profile(0) # Enable the corresponding RAM profile
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# Profile 0 is the default
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dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,
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step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
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self.cpld.io_update.pulse_mu(8)
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dds.amplitude_to_ram(self.amp, self.asf_ram)
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dds.write_ram(self.asf_ram)
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self.core.break_realtime()
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dds.set(frequency=5*MHz, phase=0.0, ram_destination=RAM_DEST_ASF)
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# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
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dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
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self.cpld.io_update.pulse_mu(8)
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.cpld.init()
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self.init_dds(self.dds0)
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self.init_dds(self.dds1)
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self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
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self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
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self.configure_ram_mode(self.dds0)
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self.configure_ram_mode(self.dds1)
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@ -0,0 +1,37 @@
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from artiq.experiment import *
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from scipy import signal
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import numpy
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class SUServoExample(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.suservo = self.get_device("suservo0")
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self.suschannels = [
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self.get_device("suservo0_ch0")
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]
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@kernel
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def run(self):
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self.core.reset()
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self.core.break_realtime()
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self.suservo.init()
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self.suservo.set_pgia_mu(0, 0) # unity gain
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self.suservo.cplds[0].set_att(0, 15.)
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self.suschannels[0].set_y(profile=0, y=0.) # Clear integrator
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self.suschannels[0].set_iir(
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profile=0,
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adc=0, # take data from Sampler channel 0
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kp=-1., # -1 P gain
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ki=0./s, # no integrator gain
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g=0., # no integrator gain limit
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delay=0. # no IIR update delay after enabling
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)
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self.suschannels[0].set_dds(
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profile=0,
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offset=-.3, # 3 V with above PGIA settings
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frequency=10*MHz,
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phase=0.)
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# enable RF, IIR updates and set profile
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self.suschannels[0].set(en_out=1, en_iir=1, profile=0)
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self.suservo.set_config(enable=1)
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