examples: move SPI examples to spi.py
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2245.tex
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2245.tex
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@ -621,13 +621,13 @@ The following examples will assume the SPI communication has the following prope
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\item Full duplex
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\end{itemize}
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The base line configuration for an \texttt{SPIMaster} instance can be defined as such:
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\inputcolorboxminted[0]{firstline=105,lastline=110}{examples/ttl.py}
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\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
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The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
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\subsubsection{SPI frequency}
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Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257].
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In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
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\inputcolorboxminted[0]{firstline=112,lastline=112}{examples/ttl.py}
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\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
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\subsubsection{SPI write}
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Typically, an SPI write operation involves sending an instruction and data to the SPI slaves.
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@ -654,7 +654,7 @@ The timing diagram of such write operation is shown in the following.
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\newpage
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Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code.
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\inputcolorboxminted{firstline=119,lastline=128}{examples/ttl.py}
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\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
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\subsubsection{SPI read}
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A 32-bits read is represented by the following timing diagram.
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@ -679,7 +679,7 @@ A 32-bits read is represented by the following timing diagram.
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\end{center}
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Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
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\inputcolorboxminted{firstline=136,lastline=150}{examples/ttl.py}
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\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
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\newpage
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\section{Ordering Information}
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@ -0,0 +1,49 @@
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from artiq.experiment import *
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
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0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY |
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0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
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0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
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CLK_DIV = 125
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class SPIWrite(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110)
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self.spi.write(0x13 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110)
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self.spi.write(0xDEADBEEF)
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class SPIRead(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001)
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self.spi.write(0x81 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, CLK_DIV, 0b001)
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self.spi.write(0) # write() performs the SPI transfer.
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# As suggested by the timing diagram,
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# the exact value of this argument
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# does not matter.
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print(self.spi.read())
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@ -101,50 +101,3 @@ class ClockGen(EnvExperiment):
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def run(self):
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self.core.reset()
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self.ttl0.set(62.5*MHz)
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from artiq.coredevice import spi2 as spi
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SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
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0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY |
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0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
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0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
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CLK_DIV = 125
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class SPIWrite(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110)
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self.spi.write(0x13 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110)
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self.spi.write(0xDEADBEEF)
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class SPIRead(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.spi = self.get_device("dio_spi0")
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@kernel
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def run(self):
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self.core.reset()
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self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001)
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self.spi.write(0x81 << 24) # Shift the bits to the MSBs.
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# Since SPI_LSB_FIRST is NOT set,
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# SPI Machine will shift out bits from
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# the MSB of the `data` register.`
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self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, CLK_DIV, 0b001)
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self.spi.write(0) # write() performs the SPI transfer.
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# As suggested by the timing diagram,
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# the exact value of this argument
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# does not matter.
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print(self.spi.read())
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